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Low-PLS global shutter pixel structure and driving time sequence control method thereof

A technology of global shutter and pixel structure, applied in image communication, TV, color TV components and other directions, can solve the problems of high design difficulty, small pixel fill factor, complex working sequence, etc., and achieve simple pixel structure and working sequence, The effect of eliminating parasitic electrons and improving efficiency

Active Publication Date: 2021-08-17
WILL SEMICON (SHANGHAI) CO LTD
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Problems solved by technology

[0004] In the traditional charge domain 5T and 6T global shutter pixels, the storage nodes FD and SDPLS are relatively high. For the voltage domain 7T and 8T global shutter pixels, although the PLS effect is suppressed to a certain extent, due to the introduction of capacitor nodes, the pixel fill factor is small. And the working sequence is complicated, and the design is difficult

Method used

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  • Low-PLS global shutter pixel structure and driving time sequence control method thereof
  • Low-PLS global shutter pixel structure and driving time sequence control method thereof

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Embodiment Construction

[0028] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0029] Embodiments of the present invention provide a low PLS global shutter pixel structure, such as figure 1 As shown, it mainly includes: seven NMOS transistors, a photodiode PD, and three storage nodes; where:

[0030] The first NMOS transistor is a reset switch transistor, its gate is connected to the reset signal RST, its drain is connected to VDD, and its source is connected to the third storage node FD;

[0031] The gate of the second NMOS...

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Abstract

The invention discloses a low-PLS global shutter pixel structure and a driving time sequence control method thereof, which can eliminate parasitic electrons during exposure in a reading process and can effectively improve the efficiency of a global pixel shutter through structural improvement and matching with a corresponding driving time sequence control scheme. Compared with a traditional global shutter pixel structure, the global shutter pixel structure has the advantages that the pixel PLS effect can be effectively suppressed, the pixel structure and the working time sequence are simple, and a large fill factor and non-consistent noise suppression are considered.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a low PLS global shutter pixel structure and a driving timing control method thereof. Background technique [0002] Global shutter CMOS image sensors are widely used in high-speed machine vision, industrial measurement, aerospace, military applications and other fields due to their low image distortion. [0003] For global shutter pixels, PLS (Parasitic Light Sensitivity, parasitic light sensitivity) is an important index to measure the consistency of imaging. PLS is defined as the sensitivity of the signal change on the storage node within the signal readout time. For a CIS with a certain array size, it takes a certain amount of time to read out the overall pixel. The larger the area array is, the longer the readout time is. Therefore, there is a time difference between the readout of the first pixel and the readout of the last pixel. During this time difference, the leakage ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N5/359
CPCH04N25/626
Inventor 龚雨琛旷章曲陈多金王菁伍建华张帅徐冰刘志碧陈杰
Owner WILL SEMICON (SHANGHAI) CO LTD
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