Method, system and verification platform for verifying chip of system on chip

Abstract

The method for verifying the chip of the system-on-chip comprises the following steps: establishing a part library comprising an interface protocol part, a bus protocol part and a verification part; creating a control file to control the verification platform, wherein the control file comprises control parameters; according to verification requirements, a software library used for running of all processors of the system-on-chip chip is established, an excitation library used for corresponding assemblies in the assembly library is established, the software library comprises execution software of all the processors, and the excitation library comprises a generator capable of sending out excitation of all the universal interface protocols; based on the verification demand and the control file, establishing a script library comprising a plurality of script files, the script library comprising a verification platform control file analysis script; under the condition that the verification scene is determined, the script analyzes a control file of the verification platform to obtain a control parameter of the verification platform; according to the control parameters, required parts are selected from a part library, and required excitation is selected from an excitation library to generate a verification platform; and verifying the system-on-chip chip through the verification platform.

Description

technical field [0001] The present invention relates to verification of a chip, and more specifically, to a technology for verification of a System-on-Chip (SoC) chip. Background technique [0002] SoC (System on Chip) chip is to integrate a complete system on a single chip. Due to the exponential growth of the design scale and structural complexity of SoC chips, the system-level verification of SoC chips is facing more and more challenges in terms of verification completeness and verification efficiency. [0003] The conventional verification method is based on SV (System Verilog), an abstract high-level language for object-oriented programming, and builds a verification platform and constructs verification cases on the basis of the UVM (Universal Verification Methodology, Universal Verification Methodology) library. Automation, electronic design automation) tool for simulation verification. In this way, it is usually necessary to build a complete and complex verification...

AI Technical Summary

Problems solved by technology

This makes verification resource-intensive and takes a relatively long time

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