Interconnected bare core interface management system and initialization method thereof

Abstract

The invention relates to a bare core interface management, in particular to an interconnect bare core interface management system and an initialization method thereof. Interconnected die interface management system, including: CMU system, JTAG-Die interface and configuration network connected to CMU system; CMU system includes CMU processor and Flash connected to CMU processor, Flash is used to store software code of CMU system ; The JTAG‑Die interface is used to control the startup of the CMU program; one end of the configuration network is connected to the CMU processor in the form of peripherals, and the other end is connected to each interface to be configured through an independent bus; the CMU processor is used to execute its configuration program. It is transmitted to the function register of each interface to be configured through the configuration network and independent bus, so as to realize the configuration of the interface address translation table. The system uses the processor to realize the system initialization configuration, and converts the hardware configuration of the interface into software programming, which reduces the design difficulty, simplifies the development process, enhances the configuration flexibility, and helps to improve the system construction speed.

Description

technical field [0001] The invention relates to a bare core interface management, in particular to an interconnect bare core interface management system and an initialization method thereof. Background technique [0002] With the development of digital integrated circuits, system-on-chip (Systemon Chip, SoC, refers to the integration of multiple functional modules on the same silicon chip) has almost become a necessary solution to achieve high-performance systems, manufacturers continue to expand the scale of SoC by To meet the user's demand for product performance. However, limited by factors such as processing technology, Moore's Law (that is, the law that the number of transistors that can be accommodated on an integrated circuit doubles every 24 months) is gradually failing, which makes it difficult to expand the scale of integrated circuits on a single silicon wafer. Costs and development cycles become extremely high. [0003] The interconnected die is a general stand...

AI Technical Summary

Problems solved by technology

However, the design of the state machine belongs to the category of hardware design. Its design is difficult, the process is complicated, and the reconstruction takes a long time, which is not conducive to the rapid construction of the system.

Images