Chip back-end revision method and device based on function buffer, and computer equipment

Abstract

The invention discloses a chip back-end revision method and device based on a function buffer, computer equipment and a storage medium. The method comprises the following steps: acquiring an original list of each electronic unit in a process file; according to the original list, searching standby units of the electronic units in a preset digital process library, and generating a replacement list according to the key value pair relation between the electronic units and the corresponding standby units; analyzing the process file according to a preset design tool, and extracting a violation file in the process file; searching a target standby unit corresponding to the violation unit in the substitution list, and forming a map file according to the target standby unit and the violation file; determining a violation type of the violation file according to a preset violation rule, and generating a script file for the design tool to run according to the map file and the violation type; and running the design tool to execute the script file, so that the target standby unit replaces the violation unit to complete modification of the process file.

Description

technical field [0001] Embodiments of the present invention relate to the field of chip manufacturing, in particular to a method, device, computer equipment, and storage medium for chip backend revision based on functional buffers. Background technique [0002] In the design of modern integrated circuits, especially the design of the digital logic part, in order to prevent new problems from being found in the test after the chip is produced, a lot of spare dummy cells (spare units) are generally evenly placed in the entire digital logic area, and the chip is revised later. In the process, only a few layers of metal need to be moved to change or repair the function of the chip. [0003] As for functional changes in the digital logic part, especially the post mask ECO stage (the transistors of the chip have been processed, but the engineering modification during the transistor connection has not been done), since the position and direction of all spare units cannot be changed ...

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Problems solved by technology

[0003] As for functional changes in the digital logic part, especially the post mask ECO stage (the transistors of the chip have been processed, but the engineering modification during the transistor connection has not been done), since the position and direction of all spare units cannot be changed , so we can only rely on the existing spare unit, modify the design function by modifying the digital netlist or the corresponding EDA (Electronic design automation, electronic design automation) tool command, and correspondingly reflect the timing and timing caused by the back-end physical design. design violations etc.

How to fix issues such as timing and design violations by inserting spare cells, the traditional processing method is to modify the digital netlist according to each violation point, including finding the position of the alternate spare cell, changing the signal point of the violation point and the alternate spare cell The hierarchical connection relationship among them, etc., and repeat this process many times until the design converges. It is obvious that this ECO (Engineering Change Order, engineering modification) method is inefficient and error-prone

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