Laminated programmable parallel video signal processor for motion estimation algorithm

A video signal and motion estimation technology, applied in the field of video image coding, can solve the problems of large-scale hardware structure and flexibility limitation, and achieve the effect of improving flexibility and great flexibility

Inactive Publication Date: 2003-11-05
TSINGHUA UNIV
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  • Abstract
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Problems solved by technology

This structure is a programmable structure based on array processors. It uses 64 array processors to complete block matching operations. restricted

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  • Laminated programmable parallel video signal processor for motion estimation algorithm
  • Laminated programmable parallel video signal processor for motion estimation algorithm
  • Laminated programmable parallel video signal processor for motion estimation algorithm

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Embodiment Construction

[0032] The structural embodiment of a hierarchical programmable parallel video signal processor (PVSP) designed for motion estimation algorithms in the present invention is described in detail with reference to the drawings as follows:

[0033] The overall structure of the PVSP of the present invention is as follows image 3 Shown. It includes six parts: low-level instruction unit, parallel operation unit, data path finding unit, memory and address generation unit, high-level instruction unit, and external memory interface unit. The connection relationship of each part is as follows. The high-level instruction unit and the low-level instruction unit are connected through the control signal line; the low-level instruction unit and the parallel operation unit are connected through the data and control signal lines; the parallel operation unit and the data path finding unit are connected through a 3-way data bus; the data path finding unit is connected to the storage and The address ...

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Abstract

The invention belongs to the field of video image coding, and relates to a layered programmable parallel video signal processor for motion estimation algorithms, including a low-level instruction unit, a parallel operation unit, a data routing unit, a memory and address generation unit, a high-level instruction unit, and a high-level instruction unit. The external memory interface unit has six parts; among them, the low-level instruction unit is respectively connected with the high-level instruction unit and the parallel operation unit through the control signal line; the data routing unit is respectively connected with the parallel operation unit and the storage and address generation unit through the data bus. The invention can simultaneously realize multiple block matching algorithms in one structure, reduce the hardware overhead of the video coding system, and support other video coding algorithms.

Description

Technical field [0001] The invention belongs to the field of video image coding, and particularly relates to the design of a hierarchical programmable parallel video signal processor. Background technique [0002] Motion estimation has been adopted by all international video compression coding standards to eliminate inter-frame correlation. However, the motion estimation algorithm is not specified by these international standards and is an open part. Different coding systems can use their own different motion estimation algorithms under the premise of satisfying the syntax structure of the code stream. The block matching full search algorithm is the algorithm with the highest search accuracy in the motion estimation algorithm, but its disadvantage is that the amount of calculation is huge, which makes the traditional general-purpose processor unable to meet the requirements. In order to solve the problem of computational load, the existing work starts from two aspects. One is to ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/00G06T9/40H04N7/24
Inventor 何芸龚大年
Owner TSINGHUA UNIV
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