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Polycrystalline silicon material filling method in semiconductor device structure and preparation method of 3D NAND memory

A 3DNAND, device structure technology, applied in semiconductor devices, electric solid state devices, electrical components, etc., can solve problems affecting device performance, film formation effects, arc effects, etc.

Pending Publication Date: 2021-03-09
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Higher polysilicon / ONO stack etching selectivity is prone to substrate groove defects at the junction of the ONO stack and the substrate
Arcing is prone to occur during the subsequent high-energy film deposition, which seriously affects the performance of the device
In addition, when the polysilicon on the surface of the substrate is removed, the substrate will be etched, which will increase the surface roughness of the substrate and affect the formation of subsequent film layers.

Method used

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  • Polycrystalline silicon material filling method in semiconductor device structure and preparation method of 3D NAND memory
  • Polycrystalline silicon material filling method in semiconductor device structure and preparation method of 3D NAND memory
  • Polycrystalline silicon material filling method in semiconductor device structure and preparation method of 3D NAND memory

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Embodiment 1

[0096] This embodiment provides a polysilicon material filling method in a semiconductor device structure, such as image 3 As shown, the method includes the following steps:

[0097] S101: Provide a substrate, the substrate is divided into an array area and a peripheral area, a stack structure is formed on the front surface of the substrate located in the array area, and a channel structure is formed in the stack structure;

[0098] The aforementioned semiconductor device structure may be various semiconductor device structures that require the formation of polysilicon material layers or polysilicon contact plugs and other similar structures. In this embodiment, a 3D NAND memory is taken as an example for illustration. It should be understood that the 3D NAND memory is only exemplary and not limiting.

[0099] like Figure 4 As shown, a substrate 101 is provided, and the substrate 101 may be any suitable substrate such as a silicon substrate, a silicon-on-insulator substrat...

Embodiment 2

[0118] This embodiment provides a method for preparing a 3D NAND memory, such as Figure 12 As shown, the method includes the following steps:

[0119] S201: Provide a substrate, the substrate is divided into an array area and a peripheral area;

[0120] S202: Alternately stack sacrificial layers and insulating layers on the front surface of the substrate located in the array area to form a stack structure, the stack structure includes a core area and a step area;

[0121] S203: forming a channel hole in the core region, forming a memory layer and a channel layer in sequence on the sidewall of the channel hole, and filling a dielectric layer in the middle of the channel hole;

[0122] S204: Forming a protection layer on the surface of the step region of the stack structure and the substrate located in the peripheral region;

[0123] S205: forming a polysilicon plug on the top of the channel hole;

[0124] S206: Removing the polysilicon formed on the protective layer during ...

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Abstract

The invention provides a filling method of a polycrystalline silicon plug material in a semiconductor device structure and a preparation method of a 3D NAND memory, and the method comprises the steps:forming a channel structure in a stacked structure of an array region of a substrate, and then forming a protection layer on the side wall of the stacked structure and the surface of the substrate located in a peripheral region, wherein the protective layer has a sufficiently high etch selectivity ratio relative to polysilicon, for example, may be a carbon thin film; and forming a trench at the top of the channel structure and depositing polycrystalline silicon. When redundant polycrystalline silicon is removed, due to the fact that the etching selection ratio of the protective layer to the polycrystalline silicon is high enough, the stacked structure and the substrate cannot be etched, the defect that substrate grooves are formed in the cross section of the stacked structure and the cross section of the substrate is overcome, and the performance of the device can be improved. And the protective layer is removed through ashing treatment, so that no by-product residue exists, and meanwhile, the substrate is not damaged. The preparation method of the 3D NAND memory also adopts the method to form the polycrystalline silicon plug, so that the 3D NAND memory also has the above beneficial effects.

Description

Technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a polysilicon material filling method in a semiconductor device structure and a preparation method of a 3D NAND memory. Background technique [0002] Memory is a memory device used to store and preserve information. As the demand for integration and storage density of devices in integrated circuits continues to increase, 3D storage technology, such as 3D NAND (3D NAND) flash memory, is becoming more and more popular. . [0003] In a NAND-type 3D flash memory, memory cells are arranged in series between bit lines and ground lines. NAND flash memory with a tandem structure has a lower reading speed but a higher writing speed. Therefore, NAND flash memory is suitable for storing data. Its advantages are small size and large capacity. In SONO type 3D NAND flash memory devices, doped polysilicon plugs (Plug Poly) are usually used as conductive loops ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/1157H01L27/11573H01L27/11582H10B43/35H10B43/27H10B43/40
CPCH10B43/35H10B43/27H10B43/40
Inventor 刘佳张天翼章诗
Owner YANGTZE MEMORY TECH CO LTD
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