Platform architecture design method of multi-core CPU operation mode

A technology of operating mode and platform architecture, applied in the direction of program control design, calculation, multi-program device, etc., can solve problems such as difficulty in taking into account reliability, real-time performance and CPU processing capability, and non-uniform underlying architecture of multi-core processors. Achieve the effect of improving security and system reliability, taking into account reliability, best real-time performance and flexible expansion capabilities

Pending Publication Date: 2021-03-09
BEIJING SIFANG JIBAO ENG TECH +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Solve the problem that the underlying architecture of multi-core processors in power secondary equipment is not uniform, and it is difficult to take into account reliability, real-time and CPU processing capabilities at the same time

Method used

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  • Platform architecture design method of multi-core CPU operation mode
  • Platform architecture design method of multi-core CPU operation mode
  • Platform architecture design method of multi-core CPU operation mode

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0031] figure 1 It is a schematic diagram of the multi-core CPU operation mode method, such as figure 1 As stated, the implementation steps of the multi-core enhanced hybrid processing mode include:

[0032] Step 1. After the multi-core CPU is powered on, the main core is first started.

[0033] In this step, start core0 first, that is, core0 is used as the master core, and the other three cores are used as slave cores.

[0034] Step 2, the master core wakes up the slave core.

[0035] In this step, the master core core0 wakes up the three slave cores core1, core2, and core3 in sequence.

[0036] Step 3, free combination of operating modes from the core.

[0037] In this step, three slave cores run the same operating system and applications.

[0038] Step 4, the main core runs the naked running business.

[0039] In this step, core0 runs its own naked running business program, and tasks with high real-time and reliability are run in the naked running program of core0.

...

Embodiment 2

[0043] figure 1 A schematic diagram of a method for enhancing a hybrid multi-core processing mode for a multi-core CPU, such as figure 1 Said, the steps of the method for multi-core enhanced symmetric multiprocessing include:

[0044] Step 1. After the multi-core CPU is powered on, the main core is first started.

[0045] In this step, core0 is first started, that is, core0 is used as the main core, and the other three cores are used as slave cores.

[0046] Step 2, the master core wakes up the slave core.

[0047] In this step, the master core core0 wakes up the three slave cores core1, core2, and core3 in sequence.

[0048] Step 3, free combination of operating modes from the core.

[0049] In this step, core1 of the three slave cores runs naked, core2 sleeps without running programs, core3 runs the operating system, and core1 and core3 run applications independently.

[0050] Step 4, the main core runs the naked running business.

[0051] In this step, core0 and core1...

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Abstract

The invention discloses a platform architecture design method of a multi-core CPU operation mode, and the method comprises the following steps that an isomorphic multi-core CPU firstly starts a main core, and the main core is core 0 of the isomorphic multi-core CPU; the master core awakens the slave core in the initialization stage; after the slave cores are started, the slave cores operate in anAMP / SMP mode in a combined mode; the main core runs platformized universal underlying software, the CPU is a central processing unit, the AMP is asymmetric multi-processing, and the SMP is symmetric multi-processing. The EHMP operation mode provided by the invention integrates the advantages of the traditional AMP and SMP modes, follows the principles that a naked running mode realizes a high-reliability and high-real-time function and an operating system mode realizes a non-strong real-time function, gives consideration to the reliability, real-time performance and CPU processing capability of a product, and ensures the safety of multi-core operation and the reliability of the system.

Description

technical field [0001] The invention belongs to the embedded technical field of secondary equipment of a power system, and relates to a platform architecture design method of a multi-core CPU operation mode. Background technique [0002] In power secondary equipment, with the upgrading of embedded chip technology, the use of multi-core CPU is becoming more and more common. At present, the commonly used operating modes of multi-core CPUs include AMP (Asymmetric Multi-Processing) and SMP (Symmetric Multi-Processing). In AMP mode, each core runs its own program independently, and the coupling between multiple cores is low. It can not only achieve excellent real-time performance and reliability by running naked on a single core, but also complete non-real-time task processing by running an operating system on a single core. The SMP mode can uniformly schedule multiple cores under one operating system, increasing the processing capacity of a single system by several times, and i...

Claims

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Application Information

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IPC IPC(8): G06F9/48G06F9/50
CPCG06F9/4843G06F9/5027
Inventor 胡炯袁海涛肖远清严岩蒋新成石景海张宗凯王世伟任海涛刘晓东
Owner BEIJING SIFANG JIBAO ENG TECH
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