Chip line sequence adjusting method and device and computer readable storage medium

Abstract

The invention provides a chip line sequence adjusting method and device and a computer readable storage medium, belongs to the technical field of computer chips, and solves the technical problems thata large number of signal lines of an existing chip are distributed to a plurality of layers and are manually adjusted one by one, the workload is huge, and errors are prone to occurring. The method comprises the following steps: classifying signal pins of a chip; determining an outgoing line direction of the chip; partitioning pins of the chip according to the outgoing line direction; determiningpre-adopted wiring layers in the circuit board, and performing priority ranking on the wiring layers; allocating an outgoing line channel to the pins of each partition; and according to the priorities of the signal pin categories and the priorities of the wiring layers, allocating a corresponding wiring layer for the outgoing line channel of each pin. According to the method, the design time of Layout on the CPLD chip can be greatly reduced, and the stacking utilization rate is improved; and meanwhile, the time of adjusting a netlist by an EE engineer can be saved, the accuracy of adjusting the line sequence is improved, the layer utilization rate and the single board yield can be improved, the research and development process and manpower are reduced, and the cost is saved.

Description

technical field [0001] The invention relates to the technical field of computer chips, in particular to a chip line sequence adjustment method, device and computer-readable storage medium. Background technique [0002] With the development of cloud computing applications, informatization has gradually covered all fields of society. People's daily work and life are more and more communicated through the network, the amount of network data is also increasing, and the performance requirements of the server are also higher. In a server, the PCB is an important part, and the number of components and wiring density are also increasing with the improvement of the performance of the server. The single board is getting bigger and bigger, and the layout and wiring are getting denser, which eventually leads to an increasing workload. [0003] The CPLD chip is often used on the board. This chip will connect a large number of single-wire signals from all directions on the board, and the...

AI Technical Summary

Problems solved by technology

[0004] The object of the present invention is to provide a chip line sequence adjustment method, device and computer-readable storage medium, which solves the problem that the signal lines on the existing CPLD chip come from all directions on the board, the number is large, and there is no law, and the chip supports the adjustment line. sequence, but a large number of signal lines are assigned to multiple layers, and manual adjustments one by one, the workload is huge and error-prone technical problems

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