A kind of three-dimensional structure nand ferroelectric storage unit and its preparation method

A technology of ferroelectric storage and three-dimensional structure, applied in the direction of electrical components, circuits, electric solid devices, etc., can solve problems such as interface layer degradation, improve fatigue resistance, improve storage performance and uniformity, and improve quality and uniformity Effect

Active Publication Date: 2022-02-08
XIANGTAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Another problem is that a major shortcoming of current devices is their fatigue performance ≤10 5 Cycling, the current mainstream view is that there is an interface layer degradation problem at the interface between the channel and the ferroelectric material under the cyclic electric field

Method used

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  • A kind of three-dimensional structure nand ferroelectric storage unit and its preparation method
  • A kind of three-dimensional structure nand ferroelectric storage unit and its preparation method
  • A kind of three-dimensional structure nand ferroelectric storage unit and its preparation method

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Embodiment 1

[0028] figure 1 It is a schematic cross-sectional structure diagram of a NAND ferroelectric memory cell with a three-dimensional structure provided in Embodiment 1 of the present invention.

[0029] Such as figure 1 As shown, the present embodiment provides a NAND ferroelectric memory cell, comprising: an oxide insulating layer, a channel layer, a channel buffer layer, a ferroelectric layer and a gate arranged in sequence from the inside to the outside; the channel A channel buffer layer is arranged between the ferroelectric layer and the ferroelectric layer; and / or, a gate buffer layer is arranged between the ferroelectric layer and the gate. Specifically, an oxide insulating layer, a channel layer, a channel buffer layer, a ferroelectric layer, and a gate buffer layer; or, an oxide insulating layer, a channel layer, a ferroelectric layer, and a gate buffer layer; or, an oxide insulating layer layer, channel layer, channel buffer layer and ferroelectric layer.

[0030] The...

Embodiment 2

[0040] figure 2 is a flow chart of the manufacturing method of the three-dimensional structure NAND ferroelectric storage unit provided by the second embodiment of the invention.

[0041] Such as figure 2 It is known that this embodiment provides a method for preparing a NAND ferroelectric memory unit, comprising: sequentially and alternately depositing multiple layers of insulating layers and gates on a substrate; depositing silicon oxide on the alternately deposited multiple layers of insulating layers and gates an insulating layer and an aluminum oxide insulating layer to complete the stacked gate; etching a via hole with a preset size on the stacked gate to reach the substrate; depositing a gate buffer layer, a ferroelectric layer, A channel buffer layer, a channel layer, and an oxide insulating layer; or, a gate buffer layer, a ferroelectric layer, a channel layer, and an oxide insulating layer; or, a ferroelectric layer, a channel buffer layer, a channel layer, and an...

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Abstract

A three-dimensional structure NAND ferroelectric storage unit and its preparation method, wherein the ferroelectric storage unit comprises: an oxide insulating layer, a channel layer, a channel buffer layer, a ferroelectric layer and a gate arranged in sequence from the inside to the outside A buffer layer and a gate; a channel buffer layer is arranged between the channel layer and the ferroelectric layer; and / or, a gate buffer layer is arranged between the ferroelectric layer and the gate. In the storage unit of the present invention, the buffer layer has the following effects: 1. It can induce the crystallization of the ferroelectric thin film to generate a ferroelectric phase; 2. It can reduce the adverse effects caused by the different crystallization characteristics of the channel layer and the ferroelectric layer during unified annealing and crystallization, and improve The quality and uniformity of the deposited film; 3. The buffer layer can improve the interface performance of the channel layer, reduce the leakage current, and improve the fatigue resistance of the device. Therefore, the buffer layer can improve the storage performance and uniformity of the storage unit in the three-dimensional structure as a whole, increase the storage window of the storage unit, improve the fatigue performance of the storage unit, and improve the uniformity of storage performance of multiple transistors.

Description

technical field [0001] The invention relates to the technical field of designing semiconductor memory and integration, in particular to a three-dimensional structure NAND ferroelectric memory unit and a preparation method thereof. Background technique [0002] The new hafnium oxide-based ferroelectric field-effect transistor (FeFET) is a new type of non-volatile memory that uses two polarization states of hafnium oxide-based ferroelectric materials to realize channel regulation. Compared with other traditional ferroelectric materials, such as PZT and SBT, hafnium oxide materials have CMOS process compatibility, high-K characteristics and higher integration. Since it was reported in 2011 that ferroelectricity was found in hafnium oxide-based materials, organizations and units in many countries have successively entered into this research work. However, the currently prepared devices are mainly planar structures, and hafnium oxide-based FeFETs with three-dimensional structure...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/1159H01L27/11597
CPCH10B51/20H10B51/30H10B51/50
Inventor 廖敏戴思维郇延伟杨棋钧刘兆通周益春
Owner XIANGTAN UNIV
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