ldmos device and its manufacturing method

Abstract

This patent application discloses an LDMOS device and a manufacturing method thereof. The manufacturing method includes: forming an epitaxial layer over a substrate, implanting a drift region and a well region in the epitaxial layer; forming a gate structure over part of the well region; A first mask with a first opening is formed above the epitaxial layer, and an inversion region is formed by implanting at an oblique angle of the first opening. The inversion region is doped opposite to the drain region in the drift region and is symmetrical about the drain region. At the same time, An additional doping region of the same doping type as the well region is formed in the well region through the second opening of the first mask; then the source region and the drain region are also doped in the first opening and the second opening. The advantage of this patent is that the same mask is used to form the drain region, the inversion region in the drift region, and the additional doping region in the well region with the same doping concentration as the well region, which can not only effectively increase the breakdown voltage of the device, but also reduce the The on-resistance of the device is improved, and the self-protection capability of the device is improved without adding any additional cost.

Description

technical field [0001] The present application relates to the field of semiconductor device manufacturing, and more particularly, to an LDMOS device and a manufacturing method thereof. Background technique [0002] Laterally-diffused metal-oxide semiconductor (LDMOS) devices can meet the requirements of high voltage resistance and power control, and are often used in radio frequency power circuits. like figure 1 As shown, the LDMOS device includes: a substrate 10, a well region 11 and a drift region 12 located on the substrate 10 and in contact with each other, a source region 13 located in the well region 11, a drain region 14 located in the drift region 12, and a source region 14 located in the drift region 12. Gate structure 15 on well region 11 . Taking an N-type LDMOS device as an example, the substrate 10 and the well region 11 are P-type doped, and the drift region 12 , the source region 13 and the drain region 14 are all N-type doped. In the LDMOS device, the well...

AI Technical Summary

Problems solved by technology

[0004] In the traditional process, in order to improve the electrical characteristics and self-protection ability of the LDMOS device, it is necessary to add an additional mask (mask) or use other more complicated processes during fabrication, thereby increasing the manufacturing cost of the device and reducing the production of the device efficiency

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