Power supply reset system architecture and power supply reset method thereof

Abstract

The invention discloses a power supply reset system architecture and a power supply reset method thereof. The power supply reset system architecture comprises an LPBGR, a BGR, a comparator, a 3-inputAND gate, a POR, an LV2HV circuit, a control logic module, an OSC, a frequency divider and time delay circuit, a BUF and an HV2LV circuit. An IBIAS_LP1 terminal of the LPBGR is connected with the input end of the BGR, and a POR_HV terminal of the LPBGR is connected with the input end of the BGR and is connected to the input end of the 3-input AND gate; the IBIAS_LP2 terminal of the LPBGR is connected to the input end of the OSC terminal; the VREF_LP terminal of the LPBGR is connected with the negative electrode input end of the comparator, and the output end of the BGR is connected with the positive electrode input end of the comparator and connected with the output end of the VREF terminal. According to the power supply reset system architecture and the power supply reset method thereof,the architecture is ingenious in design and reasonable in control, and stable and reliable power-on and power-off reset can be provided in various complex working scenes.

Description

technical field [0001] The invention relates to the technical field of a power reset system, in particular to a power reset system architecture and a power reset method thereof. Background technique [0002] Power On Reset circuits (POR: Power On Reset) are widely used in various SoC or MCU chips. When a circuit system is just powered on, the power supply voltage has not yet reached a stable state. At this time, each functional module in the chip, each circuit node voltage or logic has not been fully established, and is in an unknown state. It is wrong and unacceptable to start operating from this indeterminate initial state. In order to make the chip always run from a clear initial state every time it is powered on, it is necessary to use the POR circuit to generate a reset signal at the initial stage of power-on to initialize the entire chip. [0003] Reset control is also required when power is off, responding in advance, shutting down important modules, storing importa...

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Problems solved by technology

[0006] The purpose of the present invention is to provide a power reset system architecture and its power reset method, the architecture design is ingenious, the control is reasonable, and it can provide stable and reliable power-on and power-off resets in various complex working scenarios, so as to solve the above background In the technology, it is proposed that a single POR / PDR circuit cannot complete the work of chip reset, and a system is needed to reliably complete this work.

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