Hardware circuit design and method of data loading device for accelerating calculation of deep convolutional neural network and combining with main memory

Abstract

The invention relates to a hardware circuit design and method of a data loading device combined with a main memory. The hardware circuit design and method are used for deep convolutional neural network calculation acceleration. According to the device, a cache structure is specifically designed and comprises input cache and control, wherein a macro block segmentation method is applied to input ofa main memory or / and other memories, and regional data sharing and tensor data fusion and distribution are achieved; a parallel input register array for converting the data segmentation pieces input into the cache; and a tensor type data loading unit that is connected with the output of the input cache and the input of the parallel input register array. The design simplifies an address decoding circuit, saves area and power consumption, and does not influence high bandwidth of data. The hardware device and the data processing method provided by the invention comprise a transformation method, amacro block segmentation method and an addressing method for the input data, so that the requirement of carrying out algorithm acceleration by limited hardware resources is met, and the address management complexity is reduced.

Description

technical field [0001] The invention belongs to the field of computer hardware and artificial neural network algorithm deployment hardware acceleration, and the field of digital integrated circuit design, and specifically relates to a method for designing an architecture of an input system of a deep convolutional neural network hardware acceleration chip, and a device thereof. Background technique [0002] The deep convolutional neural network algorithm is composed of multiple layers of specific neuron algorithm layers and hidden layers, mainly including convolutional layers, and the main operator is convolution calculation of matrix or vector. The main characteristics of this computing task are the large amount of input data, the coupling of the input data with spatial feature information, and the data calculated by each convolution often overlaps with the already calculated data, and the input data is often data in tensor format. The required calculation data is extracted ...

AI Technical Summary

Problems solved by technology

In the inventions described in Patent Documents 1 and 3, accelerator resources are wasted due to different neural network algorithm layer sizes and data reusability, so that it is necessary to cooperate with other heterogeneous processors to help solve data-related problems, or It is to rely on deeper sub-micron high-cost advanced technology to improve performance; the storage method described in patent 3 needs to back up more data, resulting in too large a buffer size; the method of patent 2 uses reconfigurable computing ideas, although it pays great attention to saving resources and waste However, its data segmentation and arrangement methods are very complicated, and compilers need to be deployed in conjunction with advanced computing tasks to assist applications; the invention of patent 4 is too coupled with the design of the central processing unit, and the design and implementation complexity is too high

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