Device and method for verifying DDR by using FPGA prototype of SOC of solid state disk, computer equipment and storage medium

Abstract

The invention relates to a device and a method for verifying DDR by using an FPGA prototype of a SOC of a solid state disk, computer equipment and a storage medium. The device comprises the FPGA, wherein a double-edge-rate memory control logic module, an interface protocol conversion module and an FPGA double-edge-rate memory physical interface module are arranged in the FPGA, and DDR particles are connected to the FPGA double-edge-rate memory physical interface module; the double-edge-rate memory control logic module is used for outputting command data of a standard bus protocol consistent with the ASIC to the interface protocol conversion module; the interface protocol conversion module is used for converting the command data into command data of an interface protocol of the FPGA double-edge rate memory physical interface module and sending the command data; and the FPGA double-edge rate memory physical interface module is used for sending the received command data to the DDR particles. According to the device and the method, the FPGA double-edge-rate memory physical interface module sends the data to the DDR particles, the double-edge-rate memory control logic module of the ASICcan be verified on the FPGA, the flexibility is high, and the cost is lower.

Description

technical field [0001] The invention relates to the field of solid-state hard disks, and more specifically refers to a device, a method, a computer device and a storage medium for a solid-state hard disk SOC chip FPGA prototype verification DDR. Background technique [0002] During the SOC chip verification process of SSD (Solid State Drive, solid state drive), the SOC chip generally includes a DDR SDRAM (double date rate synchronous dynamic random access memory, double date rate synchronous dynamic random access memory) control unit, generally DDR Controller (Memory Controller, memory control logic) and DDR PHY (Physical Interface, physical layer interface), FPGA (Field-Programmable GateArray, field programmable logic gate array) prototype verification, because PHY is only used for ASIC (application-specific integrated circuit) , cannot be integrated into FPGA. DDR PHY is responsible for data transmission with low risk; mainly DDR controller is responsible for bus arbitrat...

AI Technical Summary

Problems solved by technology

[0003] For FPGA prototype verification, the traditional method is to directly use the DDR IP of the FPGA. The disadvantage of this is that the DDR Controller of the ASIC cannot be verified on the FPGA. It can only be guaranteed by EDA simulation, and the risk is high.

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