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A Method of Execution of Vector Storage Instruction with Abnormal Return

A technology of storing instructions and returning with exceptions, which is applied in the direction of machine execution devices, register devices, instruments, etc., can solve the problems of not being able to make full use of the memory access parallelism of the storage system, increasing the complexity of implementation, wasting hardware resources, and returning with exceptions. No public information and other issues to achieve the effect of reducing the implementation cost, reducing the number of channels, and improving performance

Active Publication Date: 2021-11-05
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Compared with ordinary vector storage instructions, the implementation difficulties of this type of instructions are as follows: 1) Multiple FLoads must be executed sequentially due to FReg dependencies, such as figure 2 As shown, it must be executed in the order of FLoad0, FLoad1, and FLoad2, which will result in the inability to fully utilize the memory access parallelism of the storage system, resulting in a decrease in the performance of the entire processor
2) Compared with ordinary vector storage instructions, there is one more source operand FReg, which will lead to an additional channel for source operands on the entire vector storage instruction execution path, which increases the complexity of implementation and wastes hardware resources
There is currently no public information on the implementation of this type of vector storage instruction with exception return

Method used

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  • A Method of Execution of Vector Storage Instruction with Abnormal Return
  • A Method of Execution of Vector Storage Instruction with Abnormal Return
  • A Method of Execution of Vector Storage Instruction with Abnormal Return

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Embodiment Construction

[0037] Such as image 3 and Figure 4 As shown, the implementation steps of the execution method of the vector storage instruction with abnormal return in this embodiment include:

[0038] 1) The vector storage instruction FLoad with exception return is fetched from the instruction buffer, and this process is the same as the prior art realized by the microprocessor.

[0039] 2) Split the vector storage instruction FLoad with exception return into two micro-operations, the first micro-operation is the storage operation FLoad_t, and the second micro-operation is the exception information calculation operation FALU;

[0040] 3) Parse operand information in units of micro-operations;

[0041] The first micro-operation FLoad_t split from the vector storage instruction FLoad needs to be decoded to find out that the micro-operation has two source registers and two destination registers. For the second micro-operation FALU, decoding needs to resolve that the micro-operation has two...

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PUM

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Abstract

The invention discloses an execution method of a vector storage instruction with abnormal return, the steps include taking out the instruction from the instruction buffer; splitting the vector storage instruction with abnormal return into two micro-operations: the first micro-operation is a storage operation, The second micro-operation is an exception information calculation operation; decoding, register renaming, dispatching and execution are performed in units of micro-operations. The first micro-operation is executed in the storage unit, retrieves the corresponding data from the storage, and outputs memory access exception information. The second micro-operation is executed in the calculation unit, receives the exception information of the first micro-operation and calculates a new exception register value. The invention can be used for the execution of vector storage instructions with abnormal return in the design of out-of-order superscalar microprocessors, can improve the parallelism between the vector storage instructions with abnormal return, improve processor performance, and reduce source registers of instruction execution paths number, reducing the implementation cost.

Description

technical field [0001] The invention relates to the technical field of microprocessor design, in particular to an execution method of a vector storage instruction with abnormal return, which is used for executing the vector storage instruction with abnormal return in the design of an out-of-order superscalar microprocessor. Background technique [0002] In the scalable vector instruction, in order to enhance the parallelism of data access, a vector storage instruction with exception return is added in the instruction set, which is recorded as FLoad. The feature of this type of instruction is to perform forward-looking access to data. If the forward-looking access causes an exception, the element where the exception occurred will be recorded. For ordinary instructions, after an exception occurs, an exception needs to be reported to the system, and the system handles the exception. This type of instruction does not report an exception, but records the exception information in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30
CPCG06F9/30036G06F9/30098
Inventor 郑重孙彩霞王俊辉王永文黄立波隋兵才郭辉雷国庆郭维倪晓强
Owner NAT UNIV OF DEFENSE TECH
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