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Extensible full-random full-automatic verification method based on Systemverilog and Matlab algorithms

A verification method and fully automatic technology, applied in computer-aided design, calculation, special data processing applications, etc., can solve problems such as dragging down the system, slowing down the simulation speed of the system, and manual intervention, so as to speed up the simulation speed, reduce process information, Effects of accelerated simulation speed

Active Publication Date: 2020-01-10
BEIJING ZHILIANAN TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011]2. If the number of simulation cycles is too large, many extra files will be generated, which will drag down the entire system and cause difficulty in debugging
[0012]3. The randomization is limited. It can only simulate a specific number or specific source data. It cannot guarantee to cover all parameters and data, and it is easy to miss some extreme cases. and requires manual intervention
Due to the intervention of a graphical interface or an algorithmic language platform, it slows down the system simulation speed and requires additional platform experience
[0014]5. At present, in the field of algorithms such as communication, most of the algorithms use Matlab, so the algorithm needs to be rewritten and transplanted, and the graphical display of data in Matlab cannot be realized
Python data interface is more complicated

Method used

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  • Extensible full-random full-automatic verification method based on Systemverilog and Matlab algorithms
  • Extensible full-random full-automatic verification method based on Systemverilog and Matlab algorithms
  • Extensible full-random full-automatic verification method based on Systemverilog and Matlab algorithms

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Embodiment Construction

[0043] The present invention is roughly divided into three modules, a Systemverilog platform layer, a C middle layer and a Matlab algorithm layer. like figure 1 The figure shows the hierarchy and flow of the entire platform.

[0044] The entire platform verification process is controlled by the environment script, and all command options come from the environment script, including the test items, the number of cycles, coverage and so on.

[0045] A scalable full-random automatic verification method based on Systemverilog and Matlab algorithms. When the platform is started, the entire data flow is divided into two branches (branch 1 and branch 2 as follows), and the two branches run in parallel. The interaction is controlled by global variables, the details are as follows:

[0046] The environment control part generates all required configuration parameters and original data to be tested according to the given or randomly generated random seeds, and according to all the set c...

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Abstract

The invention discloses an extensible full-random full-automatic verification method based on Systemverilog and Matlab algorithms. The whole verification method is divided into two branches, and the two branches operate in parallel, and mutual interaction depends on global variable control, wherein the environment control part generates all required configuration parameters and original to-be-tested data according to given or immediately generated random seeds and all set constraints, and the first branch is a model path, and the second branch is a real data path. Through parallel calculationof the two paths, a correct result can be obtained no matter which path is calculated by a simulation tool firstly, and all simulation time is consumed in a real data path, and a model path only occupies some simulation CPU calculation time, so that the simulation speed is greatly increased.

Description

technical field [0001] The present invention relates to a scalable full-random automatic verification method based on Systemverilog and Matlab algorithms, more specifically a simulation platform built using Systemverilog language as the environment language, calling the C intermediate interface layer model through DPI-C, and then Fully automatic by calling C-Matlab API, no additional file overhead, no graphics, no intervention full random verification method. Background technique [0002] In many integrated circuit fields, it is necessary to use the algorithm model for circuit function verification, so as to ensure that the realization of the hardware circuit is completely consistent with the realization of the algorithm. Such as communications, artificial intelligence, etc. And most of the current algorithm models are implemented in languages ​​such as Matlab. Such circuit verification methods mainly focus on the following aspects: [0003] 1. Use the standard UVM (Unive...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/398
Inventor 杨澍宁吕悦川钱炜
Owner BEIJING ZHILIANAN TECH
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