A kind of semiconductor structure and its manufacturing method

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of DVC performance degradation, large graphic distortion, small process window, etc., to reduce film consumption, reduce contour deformation, The effect of reducing graphic distortion

Active Publication Date: 2022-05-17
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a semiconductor structure and its manufacturing method, which is used to solve the problem that the critical dimension process window of the hard mask opening in the prior art is small, which is not conducive to precise control of the hard mask. critical dimension of the film opening to achieve the target critical dimension, which in turn leads to the problem of higher graphics distortion and lower DVC performance

Method used

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  • A kind of semiconductor structure and its manufacturing method
  • A kind of semiconductor structure and its manufacturing method
  • A kind of semiconductor structure and its manufacturing method

Examples

Experimental program
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Effect test

Embodiment 1

[0066] A method for fabricating a semiconductor structure is provided in this embodiment, please refer to Figure 4 , shown as a process flow diagram of the method, comprising the following steps:

[0067] S1: Provide a substrate, and form a hard mask laminate with a deposition temperature gradient in the thickness direction on the substrate, the hard mask laminate includes at least two hard mask layers, and the different hard masks The film layer corresponds to different deposition temperatures;

[0068] S2: forming an opening in the hard mask stack, the opening exposes the upper surface of the substrate, and the size of the top end of the opening is different from the size of the bottom end;

[0069] S3: Using the hard mask stack with the opening as a mask, forming a recess structure in the substrate.

[0070] See first Figure 5 , performing step S1: providing a substrate 201, and forming a hard mask stack 202 with a deposition temperature gradient in the thickness direc...

Embodiment 2

[0084] This embodiment adopts basically the same technical solution as Embodiment 1, except that in Embodiment 1, the deposition temperature of the hard mask stack in the thickness direction decreases sequentially from bottom to top, and the width of the opening The gradient decreases from top to bottom, and in this embodiment, the deposition temperature of the hard mask stack in the thickness direction increases sequentially from bottom to top, and the width of at least one section of the opening gradually increases from top to bottom. Big.

[0085] see Figure 10 , performing step S1: providing a substrate 301, and forming a hard mask stack 302 on the substrate with deposition temperature gradients varying in the thickness direction.

[0086] Specifically, the substrate 301 can be a single-layer material or a multi-layer material, for example including Si layer, SiO 2 layer and at least one of SiN layer. In this embodiment, the substrate 301 includes two kinds of material...

Embodiment 3

[0099] This embodiment adopts basically the same technical solution as Embodiment 1 or Embodiment 2. The difference is that the same etching conditions are used in Embodiment 1 and Embodiment 2 to etch each of the hard mask stacks. A hard mask layer, the width of the opening changes in a gradient in the thickness direction, and in this embodiment, at least two sections of the opening adopt different etching conditions, wherein at least one section has a width in the thickness direction It has a gradient change, and the bottom section has a vertical side wall.

[0100] see Figure 15 , which is shown as the correlation result graph of hard mask (HM) density, hard mask opening critical dimension (CD) and hard mask deposition temperature, where DZ refers to heating with a dual zone heater (Dual Zone Heater). It can be seen from the figure that the density of HM is negatively correlated with the deposition temperature, and the CD of HMO is positively correlated with the depositio...

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Abstract

The present invention provides a semiconductor structure and a manufacturing method thereof. The method includes the following steps: providing a substrate, forming a hard mask laminated on the substrate with deposition temperature gradient changes in the thickness direction, and the hard mask laminated The layer includes at least two hard mask layers, and different hard mask layers correspond to different deposition temperatures; an opening is formed in the hard mask stack, and the opening exposes the upper surface of the substrate, And the size of the top end of the opening is different from the size of the bottom end; using the hard mask stack with the opening as a mask to form a recessed structure in the substrate. The invention can expand the expected CD process window, accurately control the target CD, and is beneficial to reduce the film thickness of the hard mask layer, reduce the deformation of the opening contour of the hard mask, thereby reducing the graphic distortion and improving the DVC performance.

Description

technical field [0001] The invention belongs to the field of semiconductor integrated circuits, and relates to a semiconductor structure and a manufacturing method thereof. Background technique [0002] In three-dimensional (3D) technology, the fabrication of channel holes (English: channel hole) is a key process. To obtain a high-precision critical dimension (English full name: Critical Dimension, referred to as CD), in order to reduce distortion and improve DVC performance (an indicator of distortion, English full name: Dark Voltage Contract). Currently, a conventional hard mask (full name in English: Hard Mask, HM for short) film and a further fine-tuning etching process are provided to obtain the expected critical dimension of the channel. [0003] However, etching tools are susceptible to different RF hours (RF hours), so that different CD results are obtained. This offset (short MWBC (English full name: mean wafers between cleans)) problem will affect the comprehensiv...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/311H01L21/3213
CPCH01L21/31144H01L21/32139
Inventor 羅興安封铁柱张高升万先进
Owner YANGTZE MEMORY TECH CO LTD
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