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Architecture and method for carrying out multiply-add operation on floating-point numbers or fixed-point numbers

A floating-point number and addition operation technology, which is applied in the direction of electrical digital data processing, digital data processing components, calculations, etc., can solve the problems of single-precision or half-precision floating-point operations, low precision, and incompatibility between precision and efficiency. To achieve the effect of avoiding the decline of calculation accuracy, high adaptability and improving calculation efficiency

Active Publication Date: 2019-11-12
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The existing in-memory computing methods have shown the advantages of saving power consumption and high data bandwidth, but there are still problems of low precision, low efficiency, or incompatibility between precision and efficiency, which is far from reaching the single-precision or half-precision floating-point calculation. point arithmetic requirements

Method used

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  • Architecture and method for carrying out multiply-add operation on floating-point numbers or fixed-point numbers
  • Architecture and method for carrying out multiply-add operation on floating-point numbers or fixed-point numbers
  • Architecture and method for carrying out multiply-add operation on floating-point numbers or fixed-point numbers

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Embodiment 1

[0044] figure 1 It is a schematic diagram of the architecture for multiplying and adding floating-point numbers in Embodiment 1 of the present invention.

[0045] Such as figure 1 As shown, the architecture 100 for multiplication and addition of floating-point numbers includes a buffer memory 1a, a plurality of digital-to-analog converters 2, a computing unit array 3a, a plurality of analog-to-digital converters 4, a dislocation adder 5, and a floating-point control and arithmetic unit module 6a and the external input and output interface 7.

[0046] The buffer memory 1a is used for buffering externally input data and intermediate calculation results, that is, for buffering a plurality of input floating-point numbers and intermediate results. The cached floating-point numbers contain floating-point exponents and floating-point mantissas.

[0047] In this embodiment, the buffer memory 1a is a memory with high-speed access, which can output multi-bit data at the same time. T...

Embodiment 2

[0109] In the second embodiment, for the same structures as those in the first embodiment, the same symbols are used and the same descriptions are omitted.

[0110] Figure 14 It is a structural block diagram of the architecture for multiplying and adding floating-point numbers in Embodiment 2 of the present invention.

[0111] Such as Figure 14 As shown, the architecture 200 for multiplication and addition of floating-point numbers includes a buffer memory 1b, a plurality of digital-to-analog converters 2, a computing unit array 3b, a plurality of analog-to-digital converters 4, a dislocation adder 5, and a floating-point control and arithmetic unit module 6a and the external input and output interface 7.

[0112] In this embodiment, the bit width of the buffer memory 1b is equal to the sum of the required bit width of 2 floating-point exponents and the required bit width of 2 floating-point mantissas. and floating point numbers A i index (E Ai ), A i mantissa (M A...

Embodiment 3

[0117] In the third embodiment, for the same structures as those in the first embodiment, the same symbols are used and the same descriptions are omitted.

[0118] Figure 16 It is a structural block diagram of an architecture for multiplying and adding fixed-point numbers in Embodiment 3 of the present invention.

[0119] Such as Figure 16 As shown, the architecture 300 for multiplication and addition of fixed-point numbers includes a buffer memory 1c, a plurality of digital-to-analog converters 2, a computing cell array 3c, a plurality of analog-to-digital converters 4, a dislocation adder 5, a fixed-point controller module 6b, and an external Input and output interface 7.

[0120] In this embodiment, the buffer memory 1c is a fixed-point buffer memory, which is used to buffer and store a plurality of input fixed-point numbers and calculated fixed-point multiplication and addition results. The bit width of the fixed-point buffer memory is the required bit width of one fix...

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Abstract

The invention provides an architecture for carrying out multiply-add operation on floating-point numbers or fixed-point numbers. The architecture is characterized by comprising a buffer memory used for carrying out buffer storage on a plurality of input floating-point numbers or fixed-point numbers, the floating-point numbers comprising floating-point indexes and floating-point mantissas; a computing unit array, comprising a plurality of multiplication unit columns at least comprising one multiplication unit, and each multiplication unit column being connected to one addition unit; a floatingpoint control and arithmetic unit module, at least comprising an exponential arithmetic unit, a mantissa shift summator and a shift corrector; and an external input / output interface, used for inputting the floating-point number into the buffer memory or outputting a floating-point multiply-add result. The architecture can be expanded to any precision, and both the calculation efficiency and the calculation precision are considered. Meanwhile, the method is compatible with various memory structures and has extremely high adaptability. The architecture can be changed into any precision fixed-point number operation in the memory through proper modification.

Description

technical field [0001] The invention relates to a structure and a method for performing multiplication and addition operations of floating-point numbers or fixed-point numbers in a memory. Background technique [0002] Today's mainstream computer architecture is the von Neumann structure, and the computer is divided into a processor and a memory, and the two are connected through a data bus. The data is stored in the memory. If the data needs to be calculated, the data needs to be read from the memory, passed through the bus, and transferred to the processor for calculation. With the rise of big data and artificial intelligence, data processing requires large-scale parallel computing, and the traditional von Neumann structure will face the problems of storage walls and power consumption walls, which cannot be well adapted to the development of today's technology. [0003] In the fields of scientific computing and high-performance computing, the core operations are often flo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/57
CPCG06F7/57Y02D10/00
Inventor 解玉凤王渝胡显武冯佳韵闫石林吴丹青
Owner FUDAN UNIV
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