A method for extracting parasitic interconnection capacitance around the gate of a source-drain raised fdsoi device

Abstract

The invention discloses a gate-around parasitic interconnection capacitance extraction method for a source-drain raised FDSOI device. According to the method, the de-embedding structure of the source-drain contact hole in the shallow trench isolation region (CT-on-STI for short) can be utilized to remove the influence of active region capacitance Cf and gate and source-drain raised region parasitic capacitance Cp-RSD on the extraction of gate-around parasitic interconnection capacitance and source-drain contact hole parasitic capacitance Cco and the parasitic capacitance Cpm of the first layermetal on the gate and source-drain contact hole, and the values of the gate-around parasitic interconnection capacitance Cco and Cpm of the source-drain raised FDSOI device are accurately obtained with the help of a three-dimensional finite element simulation tool through the structure of the source-drain contact hole in the raised source-drain region (CT-on-RSD for short) so that the model of the gate-around parasitic interconnection capacitance is accurately established in a map parasitic extraction tool and the phenomenon of repeated extraction of the interconnection capacitance Cco and the Cpm in the process of extracting the gate-around parasitic capacitance can be avoided.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and in particular relates to a method for extracting parasitic interconnection capacitance around a gate of a source-drain raised FDSOI device. Background technique [0002] With the development of semiconductor process nodes to the deep submicron or nanometer level, the feature size of the device is continuously reduced, the short channel effect (Short Channel Effects, referred to as SCEs) of the traditional planar bulk silicon MOSFET device is continuously intensified, and the leakage current of the device is increasing. Large, threshold voltage fluctuations, and subthreshold characteristic degradation are becoming more and more obvious. Fully-Depleted Silicon-on-Insulator (FDSOI) devices have attracted much attention in recent years due to their good isolation from the substrate, compatibility with CMOS processes, and small parasitic capacitance. focus on. When the process node is develope...

AI Technical Summary

Problems solved by technology

However, during the test, due to the active area capacitance C f and C p-RSD and interconnect capacitance C co and C pm etc. cannot be accurately separated, which will cause SPICE models and LPE tools to co and C pm Repeated extractions, thus compromising the accuracy of the circuit simulation

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