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A kind of vertical stack package chip and preparation method thereof

A vertical, chip-loading technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve difficult and complex problems, and achieve the effect of solving the size problem of IC products

Active Publication Date: 2021-04-02
SOUTH UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] In the diversified, high-density, hybrid integrated system-in-package (SiP), the size of the entire IC product is a very important consideration. How to effectively realize the performance of the IC in the smallest three-dimensional space is a key issue for modern circuit designers and packaging technicians. The focus of thinking, but from the perspective of packaging personnel, the difficulty of its process realization is more and more complicated

Method used

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  • A kind of vertical stack package chip and preparation method thereof
  • A kind of vertical stack package chip and preparation method thereof
  • A kind of vertical stack package chip and preparation method thereof

Examples

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Embodiment 1

[0035] This embodiment provides a multilayer substrate and its preparation method, such as Figure 1-6 shown. The multilayer substrates of this embodiment are connected by connecting pins, and the multilayer substrates are prepared as follows:

[0036] 1. Packaging and interconnection structure design and production:

[0037] 1) Substrate manufacturing: figure 1 It is shown as a side view of substrate A, including upper ink layer 1-1a, circuit layer 1-2b, lower ink layer 1-1b, core board layer 1-3; through-hole annular pad 1-4, connection holes for upper and lower circuit layers And interconnect pinholes 1-5, which can be obtained by laser drilling or mechanical drilling.

[0038] figure 2 It is shown as a side view of substrate B, including upper ink layer 2-1a, circuit layer 2-2b, lower ink layer 2-1b, core board layer 2-3; circular pad 2-4, connection hole 2 of upper and lower circuit layers -5, round or square pads 2-6, used to connect with other PCB boards.

[0039...

Embodiment 2

[0051] This embodiment provides a multilayer substrate and its preparation method, such as Figure 7-10 shown.

[0052] The multi-layer substrate in this embodiment is connected by a flexible board to realize information transmission, and the flexible board includes an ink part and first welding points and second welding points located on both sides of the ink part. The multi-layer substrate includes a substrate A at the bottom, a substrate B at the top, and a plurality of connecting copper columns vertically arranged between the substrate B and the substrate A, and a soft board arranged between the substrate B and the substrate A, so The first welding point of the flexible board is connected to the substrate B, and the second welding point is connected to the substrate A, and the area of ​​the substrate B is different from that of the substrate A. By adjusting the height of the copper pillars, the substrate B and the substrate A can be adjusted.

[0053] The whole process o...

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Abstract

A vertical stack package chip comprises: a first substrate, a second substrate, ..., and an nth substrate, wherein n>1; and a plurality of connectors interconnecting the adjacent substrates, the connectors being connection pins or flexible boards, the hollow space between the adjacent substrates being adjusted by controlling the depth of the connectors placed in the substrates, or the height of the connectors. The vertical stack package chip solves the technical problem of space limitation of the original chip structure, fully utilizes the three-dimensional space of the substrate, achieves interconnection communication among multiple layers of substrates and improves the flexibility of the chip structure.

Description

technical field [0001] The invention relates to the field of chip packaging and interconnection, and more specifically relates to system-level chip packaging technology. Background technique [0002] In the diversified, high-density, hybrid integrated system-in-package (SiP), the size of the entire IC product is a very important consideration. How to effectively realize the performance of the IC in the smallest three-dimensional space is a key issue for modern circuit designers and packaging technicians. The focus of thinking, but from the perspective of packaging personnel, the process is more difficult and more complicated. Therefore, in many cases, the realization of packaging technology has become the key to diversified, high-density, hybrid integrated system-in-package. Contents of the invention [0003] In order to overcome the deficiencies of the prior art and avoid the space limitation of the original chip structure, the present invention provides a vertically sta...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/538H01L21/768
CPCH01L21/76898H01L23/5384H01L23/5386
Inventor 李俊叶怀宇刘旭裴明月张国旗
Owner SOUTH UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA
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