Neural network acceleration method and device based on pulsation array, computer equipment and storage medium

Abstract

The invention relates to the field of model construction, and a filter and a feature map are segmented according to a preset rule when a convolution step length is not 1, and the convolution is enabled to be equivalent to a convolution with a step length of 1 so as to be adaptive to a pulsation array. The invention particularly discloses a neural network acceleration method and device based on a pulse array, computer equipment and a storage medium. The method comprises the steps of acquiring convolution parameters of a convolution filter; if the convolution step length is not 1 and the size ofthe convolution filter is greater than 1 * 1, segmenting a plurality of sub-filters from the convolution filter according to a preset filter segmentation rule; obtaining a to-be-convolutional featuremap and segmenting a plurality of feature sub-maps from the to-be-convolutional feature map according to a preset feature map segmentation rule; based on the pulsation array, carrying out convolutioncalculation on the characteristic sub-graphs corresponding to the sub-filters according to the sub-filters, wherein the step length of convolution calculation is 1; and superposing convolution calculation results corresponding to the sub-filters, and outputting the result of superposition as a result of convolution calculation of the to-be-convolutional feature map by using the convolution filter.

Description

technical field [0001] The present application relates to the technical field of neural networks, and in particular to a neural network acceleration method, device, computer equipment and storage medium based on a systolic array. Background technique [0002] The most important part of the commonly used neural network is the calculation of convolution. In the convolution calculation, the convolution filter is often not equal to 1. In this case, some mainstream neural network computing libraries, such as CUDNN (NVIDIA The deep network computing library) will be significantly slower when computing this convolution. Some deep learning accelerators such as Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA), dedicated network processors (network processunits, NPU), etc. are usually implemented with a systolic array structure in the convolution part. The case where the convolution filter of the filter is not equal to 1 is very unfriendly. [0003] The existing t...

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Problems solved by technology

[0004] The embodiment of the present application provides a systolic array-based neural network acceleration method, device, computer equipment, and storage medium, which can better solve the problem that the convolution calculation with a step size other than 1 will waste systolic array calculation and scheduling resources.

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