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Non-Ethernet digital signal transmission circuit based on Ethernet transceiver chip

A digital signal and transmission circuit technology, applied in the direction of electromagnetic transceivers, optical fiber transmission, transmission systems, etc., can solve the problems of increasing hardware, increasing fault points, and high cost, and achieve the effect of reducing cost, reducing the number of hardware, and simplifying the structure

Pending Publication Date: 2019-07-26
GUANGZHOU SPACEFLIGHT HAITE SYST ENG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The present invention proposes a non-Ethernet digital signal transmission circuit based on an Ethernet transceiver chip, which solves the relatively high cost of FPGA / CPLD and serial / deserializer (SerDes) in the prior art. For small systems, The cost pressure is relatively high, and the increase of hardware increases the point of failure and the problem of system instability.

Method used

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  • Non-Ethernet digital signal transmission circuit based on Ethernet transceiver chip
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Embodiment Construction

[0013] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0014] MII / GMII (Media Independent Interface / Gigabit Media Independent Interface): Media Independent Interface / Gigabit Media Independent Interface, all digital interfaces, MII mainly includes 4 data lines for sending and receiving, 1 clock line for each, and 1 signal enable for each Lines, a total of 12 signal lines, with a bandwidth of 10Mbit / s or 100Mbit / s, GMII mainly includes 8 data lines for sending and receiving, 1 clock line for each, and 1 signal enable line...

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PUM

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Abstract

The invention discloses a non-Ethernet digital signal transmission circuit based on an Ethernet transceiver chip. The circuit comprises an Ethernet transceiver chip at a local side and an Ethernet transceiver chip at a far end. The Ethernet transceiver chips at two ends are connected through an optical fiber or twisted pair. Each Ethernet transceiver chip is provided with an Ethernet interface andan MII / GMII interface, and a sending enable signal is at a high level. According to the circuit, an Ethernet transceiver chip is adopted to enable a sending enable signal of MII / GMII to be at a highlevel and to be in an effective state, an additional bunching / debunching device does not need to be added, the number of hardware is reduced, the cost is reduced, and the system is simple and stable in composition.

Description

technical field [0001] The invention relates to a non-Ethernet digital signal transmission circuit based on an Ethernet transceiver chip. The circuit is specifically applied to optical transmission equipment such as video optical transceivers, audio optical transceivers, and data optical modems. Background technique [0002] In communication, digital signals have been widely used because of their strong anti-interference ability and good confidentiality. In order to realize the remote transmission of digital signals, it is necessary to encode the digital baseband signal so that the receiving end can recover the clock, realize synchronous transmission, and accurately receive the data sent by the opposite end. At present, the hardware programmable device FPGA / CPLD is mainly used to realize this process together with the serializer / deserializer (SerDes). The cost of FPGA / CPLD and serializer / deserializer (SerDes) is relatively high, which is more suitable for larger systems. , ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04B10/40H04B1/40H04L12/02H04B10/25
CPCH04B1/40H04B10/25H04B10/40H04L12/02
Inventor 崔鲲王文明潘龙黄玮
Owner GUANGZHOU SPACEFLIGHT HAITE SYST ENG
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