RISC-V-based hybrid mixed computing system and method

Abstract

The invention discloses a RISC-V-based hybrid mixed computing system and method. The system comprises an instruction control module and a mixed calculation module, an expansion instruction is arrangedin the instruction control module, and the expansion instruction contains operation information; the instruction control module is used for automatically setting operation data and operation information in sequence and then transmitting the operation data and the operation information to the hybrid mixed calculation module through an extension instruction; and the hybrid calculation module is used for selecting a corresponding operation mode according to the operation information, performing hybrid operation by combining the operation data and the selected operation mode, and outputting an operation result. Complex hybrid operation is achieved through a single extension instruction, and some complex operations of the processor based on the RISC-V instruction set are simplified. The calculation process of complex hybrid computation is simplified; the disassembling machine code is simpler and clearer; time consumption caused by multiple times of cyclic operation is reduced, the system performance is improved, and the method can be widely applied to the technical field of communication.

Description

technical field [0001] The present invention relates to the field of communication technologies, in particular to a RISC-V-based hybrid computing system and method. Background technique [0002] RISC-V is an open source instruction set architecture designed and published by the University of California, Berkeley. The authorization model of RISC-V is BSD module. Since its official release in 2014, both schools and enterprises have joined in the research of RISC-V. Well-known universities and research institutions at home and abroad include University of Cambridge, ETH Zurich, The Indian Institute of Technology and the Chinese Academy of Sciences, while well-known companies include Google and IBM. The ecological environment surrounding RISC-V has gradually improved, and many open source processors and SOCs have emerged. RISC-V-based open source processors include: Rocket, BOOM, Z-scale, RI5CY, ZERO-RISCY, Hummingbird E200, ORCA, SCR series, YARVI, FlexPRET, PicoRV32, SHAKTI,...

AI Technical Summary

Problems solved by technology

RISC-V is still customizing the P DSP instruction set and the V vector instruction set. Although the P and V instruction control module sets are customized, there will be instructio...

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