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3D-stack CIS (CMOS Image Sensor) and bonding method thereof

A stacking and three-dimensional technology, which is applied in the field of three-dimensional stacking CIS and its bonding, can solve the problems of affecting the bonding effect and contact surface voids

Inactive Publication Date: 2019-07-05
HUAIAN IMAGING DEVICE MFGR CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] However, in the prior art, after CMP, the surface of the copper pad often has depressions. If the subsequent bonding pressure is not enough or the depression is too large, voids will appear on the contact surface after wafer bonding, affecting the bond. combined effect

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  • 3D-stack CIS (CMOS Image Sensor) and bonding method thereof

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Embodiment Construction

[0026] In the existing bonding process of the three-dimensional stacked CIS, two semiconductor substrates need to be bonded. Specifically, a logic device and a pixel device can be respectively formed in two semiconductor substrates, and then a flush copper pad is formed on the surface of the two semiconductor substrates by using a CMP process, and then a certain pressure is applied to the two semiconductor substrates. The substrates are bonded and interconnected between the copper pads.

[0027] The inventors of the present invention have found through research that in the existing CMP process, there is a problem of grinding uniformity (Uniformity) due to the use of grinding fluid containing grinding particles for grinding. There are more abrasive particles and the grinding rate is higher, so after CMP, the surface of the copper pad will often have depressions. If the subsequent bonding pressure is not enough or the depression is too large, it will cause voids on the contact s...

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Abstract

The invention relates to a 3D-stack CIS (CMOS Image Sensor) and a bonding method thereof. The method comprises the steps of providing a first semiconductor substrate and a second semiconductor substrate, wherein the front of the first semiconductor substrate is provided with a first liner, the front of the second semiconductor substrate is provided with a second liner, and the second liner and thefirst liner are in one-to-one correspondence in position; coating the surface of the first liner with a first soldering flux layer; attaching a metal ball to the surface of the first soldering flux layer; coating the surface of the second liner with a second soldering flux layer; aligning and bonding the front of the first semiconductor substrate and the front of the second semiconductor substrate; and heating the first semiconductor substrate and the second semiconductor substrate until at least part of the metal ball is melted. The scheme of the invention can effectively reduce the influence imposed on the bonding effect by holes and improve the bonding quality.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional stacked CIS and a bonding method thereof. Background technique [0002] The image sensor is the core component of the camera equipment, which realizes the image capture function by converting the optical signal into an electrical signal. Taking Complementary Metal Oxide Semiconductor Image Sensors (CMOS Image Sensors, CIS) devices as an example, due to their advantages of low power consumption and high signal-to-noise ratio, they have been widely used in various fields. [0003] 3D-Stack CIS was developed to support the demand for higher quality images. Specifically, the three-dimensional stacked CIS can separately manufacture the logic wafer and the pixel wafer, and then bond the front side of the logic wafer and the front side of the pixel wafer, because the pixel part and the logic circuit part are independent of each other. , so the p...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/146
CPCH01L27/14636H01L27/14643H01L27/14689
Inventor 马星晁阳黄晓橹张祥平伍建华
Owner HUAIAN IMAGING DEVICE MFGR CORP
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