A non-shielding interrupt processing system and method suitable for a RISC-V architecture

Abstract

The invention relates to the technical field of low-power-consumption kernel interrupt processing, in particular to a non-shielding interruption processing system and method suitable for a RISC-V architecture, and the system comprises a mode register, an abnormal vector base address register, a state register, an abnormal return address register, an abnormal reason register, a non-shielding interruption vector base address register, a non-shielding interruption state register, and a non-shielding interruption return address register. Beneficial effects are as follows: the device is simple in structure; an abnormal vector base address register is interrupted through non-shielding; the state of the processor when the non-shielding interruption occurs is stored in the non-shielding interruption state register, the values of the abnormal vector base address register and the state register are not changed, nesting of the non-shielding interruption can be recovered, and it is further guaranteed that the system can recover after the non-shielding interruption occurs.

Description

technical field [0001] The present invention relates to the technical field of low power consumption kernel interrupt processing, in particular to a non-shielding interrupt processing system and method suitable for RISC-V architecture. Background technique [0002] Non-maskable interrupt (NMI, Non-Maskable Interrupt) is a special input signal of the processor core, which is often used to indicate an emergency error at the system level (for example, external hardware failure, etc.). After encountering a non-maskable interrupt, the processor core will immediately suspend the execution of the current program, and instead process the non-maskable interrupt error. [0003] In the prior art, after a non-masked interrupt occurs in the system, the core of the processor will have the following actions: (1) jump to the non-masked interrupt vector address defined by the system to handle the non-masked interrupt error; (2) the mepc register update become the address of the next instruc...

AI Technical Summary

Problems solved by technology

In practical applications, if a non-masked interrupt occurs in an interrupt or exception service program, for the RISC-V architecture, the mepc registers automatically saved by the hardware when an interrupt occurs will be overwritten when a non-masked interrupt occurs, resulting in unrecoverable (non-recoverable)

Therefore, in the RISC-V architecture, if there is an interrupt or an unmaskable interrupt occurs in an exception, there will be an unrecoverable problem

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