A programmable logic unit structure and a chip

Abstract

The invention relates to the field of integrated circuit design, and discloses a programmable logic unit structure and a chip. The programmable logic unit structure comprises a first logic unit LE5 and a second logic unit LE4. The LE4 and the LE5 are mixed to form a programmable logic pair structure, a plurality of programmable logic pair structures are combined to form a programmable logic blockstructure, and carry chains of the LE4 in adjacent programmable logic pairs are connected to form an N-bit traveling wave addition; And carry chains of LE5 in adjacent programmable logic pairs are connected to form 2N-bit traveling wave addition. In practical application, common logic can be achieved through LE4 mapping, multi-output logic and arithmetic operation under the same input condition are achieved through LE5 mapping, and the balance of the resource area utilization rate and flexibility is achieved.

Description

technical field [0001] This application relates to the field of integrated circuit design, in particular to the technology of programmable logic unit structure design. Background technique [0002] Multiple LEs of the same structure are used in most FPGA architectures combined in one programmable logic block. Most resources such as traditional commercial FPGAs. LE4 is generated by a logic function based on a simple four-input look-up table structure and a full add. device and a DFF form. A programmable logic block contains N LE4s, such as N=8. This single LE structure wastes too many input ports when implementing addition and subtraction logic, resulting in a lot of unused interconnection resources, less combinatorial logic and addition logic that can be realized per unit chip area, and low resource area utilization efficiency. Contents of the invention [0003] The purpose of this application is to provide a programmable logic unit structure and chip, which can simplify...

AI Technical Summary

Problems solved by technology

This single LE structure wastes too many input ports when implementing addition and subtraction logic, resulting in a lot of unused interconnection resources, less combinational logic and addition logic that can be realized per unit chip area, and low resource area utilization efficiency

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