Online simulation system for necessary bit single event upset fault on SRAM type FPGA

Abstract

The invention discloses an online simulation system for a necessary bit single event upset fault on an SRAM type FPGA. The system design method belongs to the technical field of testing. The system isdesigned to be composed of an upper computer (1), namely a PC end, and a lower computer (2), namely an FPGA end. The system design of the upper computer (1) comprises a test interface (101), a necessary bit file extraction module (102), a debugging bit stream file analysis module (103) and a communication interface (104); the system design of the lower computer (2) comprises a main control module(201), a to-be-tested circuit (202), a gold circuit (203), a comparison circuit (204), a serial port communication module (205), a JTAG interface (206) and a configuration RAM (207). A test interface(101) located on an upper computer (1) sends an instruction command to a lower computer (2) to control a simulation process of single event upset fault simulation, and the lower computer (2) executescorresponding operation according to the received command and then returns a result. The method does not need participation of a processor, does not need external hardware expenditure, and can be flexibly transplanted to other ICAP-supporting FPGA chips.

Description

technical field [0001] The invention relates to an on-line simulation system for a necessary bit single event flip fault on an SRAM type FPGA, belonging to the technical field of testing. Background technique [0002] SRAM (Static Random Access Memory) FPGA (Field Programmable Gate Array) is more and more used in the aerospace field due to its advantages of low cost, rich logic resources, reconfigurability, and short development cycle. However, due to the structural characteristics of the SRAM FPGA itself, it is extremely vulnerable to the impact of high-energy charged particles in space and other radiation environments, resulting in a single event upset (Single Event Upset, SEU), which will cause bit flips in the memory cells in the FPGA. . Because the configuration RAM is the largest number of storage units in the chip, and considering the direct impact of the configuration RAM on the user circuit logic, the classification of SEU faults on the configuration RAM is particu...

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However, since the PicoPlaze processor has no official C compiler and the instruction space is extremely small (1024 words), the SEM controller cannot be flexibly reprogrammed to implement a new refresh mechanism

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