A chip mipi interface loss prevention protection circuit

Abstract

The invention discloses a chip MIPI interface damage-prevention protective circuit, which comprises a chip and an ESD protection device, wherein a clamping circuit unit is arranged between the chip and the ESD protection device, the clamping circuit unit comprises a diode, a current source and a leakage circuit, one ends of the current source and the leakage circuit are grounded, and the other ends are connected with each other and respectively connected with a set of output ends of the chip by means of diodes, thereby protecting an MIPI interface of the chip. The chip MIPI interface damage-prevention protective circuit aims at the situation that a present MIPI interface protective circuit is prone to damage an IO port of the chip, additionally arranges the clamping circuit on the basis ofthe existing protective circuit, and controls the voltage within a certain range, so as to prevent the IO port of the chip from being damaged.

Description

technical field [0001] The invention belongs to the field of signal generator interface protection, in particular to a chip MIPI interface loss prevention protection circuit. Background technique [0002] The signal generator (PG for short) needs to use the chip when generating the MIPI D PHY signal through the FPGA or the controller. Taking MC20902 as an example, its output port is sensitive to static electricity and not resistant to DC voltage. In the current equipment requirements, there will be situations where the ESD level of the MIPI output interface is required to be 8kV for contact, 15kV for air, and the interface can withstand DC voltages of 20V and below. It is difficult to meet the demand if the damage protection circuit is used. [0003] Such as figure 1 Shown is the internal structure diagram of the MC20902 chip in the prior art. Among them, the left side is the input of MC20902, there are HS (high speed) signal and LP (low speed, low power consumption) sig...

AI Technical Summary

Problems solved by technology

For example, when the VDDIO of MC20902 is 2.5V, when static electricity hits J1, the voltage on MC20902 IO is greater than 2.5V, especially the A and E channels, because they are controllable bidirectional, they are particularly sensitive to ESD and DC voltage ,easily damaged

Apply DC voltage to J1, the actual test voltage on the MC20902 IO is about 3.3V, and it basically always has 3.3V, which will easily cause the O of MC20902 to be damaged

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