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High-performance low-temperature-sintering laminated chip varistor material

A low-temperature sintering and piezoresistor technology, which is applied to piezoresistors, piezoresistor cores, etc., can solve problems such as poor performance of piezoresistor materials, achieve good application prospects, reasonable formula ratio, and improve sintering density sexual effect

Inactive Publication Date: 2019-05-24
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In view of the above existing problems or deficiencies, in order to solve the problem of poor performance of the existing low-temperature sintered laminated chip varistor materials, the present invention provides a high-performance low-temperature sintered laminated chip varistor material, in ZnO-Bi 2 o 3 Add Ta on the base varistor material 2 o 5 With borosilicate zinc bismuth glass (BBSZ), improve the grain boundary barrier and sintering compactness of the material

Method used

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Effect test

Embodiment 1

[0019] Embodiment 1: (1) adopt following raw material composition and content preparation material thereof:

[0020] Table 1: Formula table of embodiment 1 (unit: mol)

[0021] ZnO

[0022] (2) Weigh the raw materials according to the formula ratio in Table 1, mix the raw materials by ball milling, drying, crushing and sieving to obtain high-performance low-temperature sintered laminated chip varistor materials, and then prepare them according to the manufacturing process of laminated chip capacitors Chip varistors, that is, the varistor materials are prepared by slurry preparation, casting, lamination, molding, isostatic pressing, cutting, debinding, sintering, chamfering, spraying, capping, electroplating, etc., to obtain laminated varistors. Layer chip varistors, in which the thickness of the cast film is 50 μm, the isostatic pressure is 32 MPa and the pressure is maintained for 15 minutes, the sintering temperature is 915 ° C and kept for 6 hours, and then naturall...

Embodiment 2

[0023] Embodiment 2: (1) adopt following raw material composition and content preparation material thereof:

[0024] Table 2: Formula table of embodiment 2 (unit: mol)

[0025] ZnO

[0026] (2) Weigh the raw materials according to the formula ratio in Table 2, and mix the raw materials by ball milling, drying, crushing and sieving to obtain high-performance low-temperature sintered laminated chip varistor materials, and then prepare them according to the manufacturing process of laminated chip capacitors Chip varistors, that is, the varistor materials are prepared by slurry preparation, casting, lamination, molding, isostatic pressing, cutting, debinding, sintering, chamfering, spraying, capping, electroplating, etc., to obtain laminated varistors. Layer chip varistors, in which the thickness of the cast film is 50 μm, the isostatic pressure is 32 MPa and the pressure is maintained for 15 minutes, the sintering temperature is 915 ° C and kept for 6 hours, and then na...

Embodiment 3

[0027] Embodiment 3: (1) adopt following raw material composition and content preparation material thereof:

[0028] Table 3: Formula table of embodiment 3 (unit: mol)

[0029] ZnO

[0030] (2) Weigh the raw materials according to the formula ratio in Table 3, mix the raw materials by ball milling, drying, crushing and sieving to obtain high-performance low-temperature sintered laminated chip varistor materials, and then prepare them according to the manufacturing process of laminated chip capacitors Chip varistors, that is, the varistor materials are prepared by slurry preparation, casting, lamination, molding, isostatic pressing, cutting, debinding, sintering, chamfering, spraying, capping, electroplating, etc., to obtain laminated varistors. Layer chip varistors, in which the thickness of the cast film is 50 μm, the isostatic pressure is 32 MPa and the pressure is maintained for 15 minutes, the sintering temperature is 915 ° C and kept for 6 hours, and then natura...

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Abstract

The invention relates to a high-stability low-temperature-sintering laminated chip varistor material and belongs to the technical field of electronic materials. The high-stability low-temperature-sintering laminated chip varistor material has the advantages that by adding Ta2O5 and BBSZ glass into a ZnO-Bi2O3-based low-temperature-sintering varistor material and using a liquid phase sintering mechanism to accelerate a mass transfer process, the sintering compactness of the material is further increased, and the sintering temperature of the material is lowered; a chip varistor produced by the material through a laminated chip capacitor production process has a high-stability voltage-sensitive feature and is low in sintering temperature (850-925 DEG C), high in nonlinear coefficient (not smaller than 86.26), small in leakage currents and promising in application prospect.

Description

technical field [0001] The invention belongs to the technical field of electronic materials, and in particular relates to a high-performance low-temperature sintered laminated chip varistor material. Background technique [0002] The varistor is a resistive device with nonlinear volt-ampere characteristics, which is mainly used for voltage clamping when the circuit is subjected to overvoltage, absorbing excess current to protect sensitive devices. Among them, chip varistors with a laminated structure are widely used because of their small size, fast response speed, and large energy bearing capacity, and can meet the development needs of electronic components towards planarization, integration, and miniaturization. It has good development prospects in the fields of aviation, aerospace, electric power, mobile communications, automotive electronics, and household appliances. [0003] At present, the more mature inorganic materials used to manufacture multilayer chip varistors ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): C04B35/453C04B35/622C04B35/64H01C7/112H01C7/108
Inventor 李元勋陆永成彭睿陶志华
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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