Layout and wiring method suitable for improving CPU core frequency

Abstract

The invention discloses a layout and wiring method suitable for improving CPU core frequency. According to the invention, the physical realization layout and wiring method is improved; clock tree pre-synthesis is carried out in the layout stage; Useful offset (Useful Skew) and advanced on-chip change (AOCV) are used in the whole layout and wiring process (layout with clock tree pre-synthesis, clock tree synthesis and wiring). The whole process does not repair the retention time violation, resistance-capacitance coefficient correction is performed after wiring is completed, and then layout-clock tree synthesis-wiring with clock tree pre-integration is executed again. According to the invention, higher frequency of the CPU core can be realized, the area and the power consumption can be keptcontrollable, the time sequence convergence speed under multiple modes and multiple end angles is accelerated, and the method has the advantages of simple process, high operability and high time sequence convergence speed, and can still meet other sign-off tape-out conditions.

Description

technical field [0001] The invention relates to the technical field of integrated circuit electronic automation design of high-performance CPU cores, in particular to a layout and wiring method suitable for increasing the frequency of CPU cores. Background technique [0002] The physical implementation of high-performance CPU cores has always been a difficult point in microprocessor design, and the frequency of CPU cores directly affects the performance of microprocessors. How to increase the frequency of the CPU core from the layout and routing method of physical design is a subject worth studying. The main problems in the physical implementation of the CPU core under advanced technology are as follows: [0003] 1. As the chip technology enters the ultra-deep sub-micron stage, the influence of process parameters on device delay is becoming more and more prominent. The width of metal lines under advanced technology is reduced to only tens of nanometers, and at the same time...

AI Technical Summary

Problems solved by technology

The current mainstream technology has entered the nanometer stage. Using fixed on-chip variation values ​​to constrain the timing for layout and routing will lead to overly pessimistic timing, which will affect the frequency breakthrough of the CPU core.

[0007]5. In addition to concentrating on repairing setup violations, the traditional place and route method usually repairs the hold time after clock tree synthesis or during routing (hold) Violation

However, from the perspective of layout and routing methodology itself, it is rare to maximize the frequency at the minimum cost while keeping the area and power consumption controllable

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