A Timing Budget Method Considering Distance and Clock

Abstract

Aiming at the roughness and limitations of the timing budget method with the shortest boundary and the timing budget method based on logic depth in hierarchical physical design, the present invention provides a timing budget method considering distance and clock. This method fully considers the physical distance between two modules and the impact of clock skew on the timing of cross-module paths. By carefully analyzing the physical locations of module ports and related boundary registers and the logical depth of cross-module paths, and according to the interconnection Line delay calculation, logic depth ratio calculation, and clock skew estimation are used to obtain more accurate and reasonable timing budget values ​​for each module port, thereby reducing the number of iterations of cross-module path timing optimization and accelerating chip design. Timing closure in .

Description

technical field [0001] The invention relates to a timing budget method in integrated circuit back-end physical design, especially for hierarchical physical design. Background technique [0002] Timing closure is the key to today's chip design, and it is also the biggest challenge. In hierarchical design, since the physical design of the top layer and each sub-module is carried out in parallel, a key issue is to ensure the consistency of the timing convergence of the sub-modules and the timing convergence of the top layer. A better timing budget is hierarchical An important prerequisite for fast closure and consistency of physical design timing. A reasonable timing budget is conducive to the convergence of the design, on the contrary, an unreasonable timing budget will hinder the progress of the physical design of the sub-module, and then affect the entire design cycle. How to give a reasonable timing budget according to the actual situation becomes the key to hierarchical ...

AI Technical Summary

Problems solved by technology

A reasonable timing budget is conducive to the convergence of the design, on the contrary, an unreasonable timing budget will hinder the progress of the physical design of the sub-module, thereby affecting the entire design cycle

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