SEU and SET resisting DICE trigger design method based on SMIC 65nm commercial process

Abstract

The invention discloses a SEU and SET resisting DICE trigger design method based on a SMIC 65nm commercial process. Firstly, an input circuit on a DICE trigger is replaced with a stack CMOS circuit soas to realize SET resisting reinforcement design of the input circuit; then, a primary latch and a secondary latch on the DICE trigger are processed so as to reduce an operating distance between SETpulse width and a charge sharing effect and realize SEU resisting reinforcement; finally, the output circuit on the DICE trigger is replaced with a C-element circuit so as to filter the SET in the latch broadcasted to an output end. The method in the invention uses the stack CMOS circuit and the C-element circuit in cooperation with a filling MOS tube and a source isolation MOS tube to realize thecircuit design of the DICE trigger, which is high in reliability, solves the problem of large timing sequence overhead brought by using a delay filtering circuit to realize SET reinforcement, effectively improves the capability of resisting SEU and SET of the DICE trigger, and achieves a prospective protection effect and low cost.

Description

technical field [0001] The invention relates to a design method of a DICE trigger against SEU and SET based on a SMIC 65nm commercial process, and belongs to the field of CMOS integrated circuit space single-event effect protection. Background technique [0002] In the space radiation environment, CMOS integrated circuits are susceptible to single-event flipping and single-event transients. The generation of SET / SEU is that when high-energy ions are incident on the drain region of the off-state MOS transistor, electron-hole pairs will be generated on its path. Under the action of the electric field, for the NMOS tube, the electrons drift to the drain, and for the PMOS, the holes drift to the drain, thereby generating a transient pulse (SET). The energy of the pulse is collected by the positive feedback loop and changes the logic state of the feedback loop, resulting in SEU. Due to the existence of the bipolar effect of the MOS transistor, the pulse width of SET and the pro...

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Problems solved by technology

[0004] However, as the process size decreases, the influence of the charge sharing effect increases. When the process size reaches the 65nm node, it is difficult for the flip-flop based on the DICE structure to achieve the expected protection effect; at the same time, the DICE structure does not improve the anti-SET capability of the flip-flop. , in high-speed ASICs with nanotechnology, SET is more easily trapped and single-event soft errors occur

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