Reducing read disturb in memory device during signal switching transients

Abstract

A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. Select gate transistors are transitioned to a conductive state one or more time during a sensing process, at the drain and / or source ends of the memory strings in an unselected sub-block. The transitioning can occur periodically, multiple times during the sensing process. When the select gate transistors are in a conductive state, accumulated holes in the channel can be removed. This help provide a faster decrease of the channel potential when the unselected word line voltages are ramped down at the end of the sensing process. The duration of a disturb-inducing channel gradient which is created next to the edge data memory cell is reduced so that read disturb of this cell is also reduced.

Description

technical field [0001] The present disclosure relates to the operation of memory devices. Background technique [0002] The use of semiconductor memory devices in various electronic devices has become more popular. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. [0003] Charge storage materials, such as floating gates or charge-trapping materials, can be used in such memory devices to store charges representative of data states. Charge-trapping materials may be arranged vertically in a three-dimensional (3D) stacked memory structure, or may be arranged horizontally in a two-dimensional (2D) memory structure. One example of a 3D memory structure is a cost-scalable (BiCS) architecture comprising alternating conductive and dielectric layers. [0004] The memory device includes memory cells, which may be arranged in strings, ...

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Problems solved by technology

However, various challenges exist in operating such memory devices

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