Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Sensitive Amplifier Circuit

A technology of sense amplifiers and circuits, applied in amplifiers, amplifiers with field effect devices, amplifiers with only semiconductor devices, etc. Effect

Active Publication Date: 2022-06-17
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
View PDF8 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] exist figure 1 In the circuit shown, the voltage of node VE during charging is VDD-Vt, VDD is the power supply voltage, and Vt is the threshold voltage of the PMOS transistor PM1, which will affect the charging speed. In addition, when Iref and Icell are close, the latch The time for the circuit to accelerate will be longer

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Sensitive Amplifier Circuit
  • Sensitive Amplifier Circuit
  • Sensitive Amplifier Circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0027] combine image 3 As shown, the improved sense amplifier circuit of the present invention, in the following embodiments, includes: nine PMOS transistors PM1-PM9, seven NMOS transistors NM1-NM7, two capacitors C1, C2, and two inverters FX1 , FX2, an operational amplifier YF1, a voltage-controlled current source DY3 and a storage unit.

[0028] The sources of the PMOS transistors PM1 and PM4 and the drains of the PMOS transistors PM3 and PM2 are connected to the power supply voltage terminal VDD.

[0029] The source of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM1, and the connected node is denoted as LD. The source of the PMOS transistor PM2 is connected to the drain of the PMOS transistor PM4, and the connected node is denoted as RD. One end of the capacitor C1 is connected to the node LD, and the other end is connected to the gate of the PMOS transistor PM2, and the connected node is marked as RG; one end of the capacitor C2 is connected ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a sensitive amplifier circuit, comprising: nine PMOS transistors, seven NMOS transistors, two capacitors, two inverters, an operational amplifier, a voltage-controlled current source and a storage unit; the first capacitor and the The second capacitor controls the compensation current of the first PMOS transistor and the second PMOS transistor; the storage unit current and the first voltage-controlled current source current affect the compensation current through the first capacitor and the second capacitor, realizing the function of dynamically changing the compensation current. The invention can greatly increase the speed of the comparison current and realize a high-speed sensitive amplifier circuit.

Description

technical field [0001] The present invention relates to the field of semiconductor integrated circuits, in particular to a sense amplifier (SA) circuit. Background technique [0002] The traditional sense amplifier mainly realizes the effect of improving the speed through the current comparison and the method of latch acceleration. [0003] figure 1 It is an existing traditional sense amplifier circuit. It consists of four PMOS transistors PM0~PM3, six NMOS transistors NM0~NM5, two capacitors C1 and C2, two voltage-controlled current sources DY1 and DY2, and an RS trigger RS. composition. [0004] The current lref is the current flowing from the drain of the PMOS transistor PM1 and entering the node VD0; the current lcell is the current flowing from the drain of the PMOS transistor PM2 and entering the node VD1. [0005] LATCH is a latch circuit, and the reference memory cell CKDY is in figure 1 The middle is composed of a capacitor C1 and a voltage-controlled current so...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H03F3/16
CPCH03F3/165
Inventor 王鑫
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com