Gate structure and methods thereof

Abstract

The embodiment of the invention relates to a method and structure that provide a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

Description

technical field [0001] Embodiments of the present invention generally relate to the field of semiconductors, and more particularly, to gate structures and methods of forming the same. Background technique [0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices capable of simultaneously supporting more and more increasingly complex and refined functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture integrated circuits (ICs) that are low cost, high performance, and low power consumption. To date, these goals have been largely achieved by scaling down semiconductor IC dimensions (eg, minimum feature size), and thus increasing production efficiency and reducing associated costs. However, this scaling down also creates an increased complexity of the semiconductor fabrication process. Accordingly, achieving continued advances in semiconductor ICs and devices requires similar advances in...

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Problems solved by technology

[0004] Therefore, the existing process has not proven to be completely satisfactory in all respects

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