High-speed low-jitter frequency discrimination phase discriminator and clock data recovery circuit

A technology of clock data recovery and frequency and phase detector, applied in the direction of electrical components, automatic power control, etc., can solve the problems of complex PFD and inapplicable data signals, achieve a large capture range, improve tuning linearity, and save area Effect

Active Publication Date: 2019-01-04
NANJING UNIV OF POSTS & TELECOMM
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Of course, since the clock can be regarded as a special data signal, generally clock-based PFD is not suitable for data signals, but data-based PFD can be applied to clock signals, and relatively speaking, data-based PFD is more complicated many

Method used

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  • High-speed low-jitter frequency discrimination phase discriminator and clock data recovery circuit
  • High-speed low-jitter frequency discrimination phase discriminator and clock data recovery circuit
  • High-speed low-jitter frequency discrimination phase discriminator and clock data recovery circuit

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Embodiment Construction

[0038] The present invention will be further described below in conjunction with the accompanying drawings.

[0039] like figure 1 Shown is a brand-new frequency and phase detector, which can retain the fast frequency acquisition capability of Bang-Bang PFD, and can also obtain low jitter performance in the phase detection stage after frequency locking.

[0040] refer to Figure 7 It is a high-speed and low-jitter frequency and phase detector of the present invention. Frequency and phase detectors include Q-channel Bang-Bang-type PDs (DFF6, DFF7, DFF8), I-channel Bang-Bang-type PDs (DFF1, DFF3, DFF5), three-state output FD and two DFFs (DFF2 and DFF4 ), two XORs (used to form Alexander PD). Among them, the Bang-Bang type PD of Q road, DATA IN with CLK Q As the input signal of DFF6 and DFF7, CLK Q Connect to DFF6 in reverse. DFF8 samples the output of DFF6 on the falling edge of DFF7; DATA in the Bang-Bang type PD of I channel IN with CLK I As the input signal of DFF1...

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Abstract

The invention discloses a high-speed low-jitter frequency discrimination phase discriminator and a clock data recovery circuit. The frequency discrimination phase discriminator comprises a Q-channel Bang-Bang-type PD generating a Q-channel signal, an Alexander PD generating an I-channel signal and a tri-state Output FD; the Q-channel Bang-Bang-type PD includes DFF6, DFF7, and DFF8; the Alexander PD includes DFF1, DFF2, DFF3, DFF4, DFF5, XOR1, and XOR2, where DFF1, DFF3, and DFF5 constitute an I-channel Bang-Bang type PD; the three-state output FD includes Latch1, Latch2, and a three-state selector. The Alexander PD in the present invention is additionally provided with two DFFs and two XORs based on the Bang-Bang type PD. The FD consists of the two latches and the three-state selector. ThePFD of the present invention can perform the frequency acquisition function quickly in the frequency discrimination process, and the phase tracking process of the Alexander PD after the frequency lock.

Description

technical field [0001] The invention relates to a high-speed and low-jitter frequency and phase detector and a clock data recovery circuit to improve loop performance, which belongs to the design technology of semiconductor integrated circuits. Background technique [0002] Phase Frequency Detector (PFD for short) detects and judges the input data signal and the clock signal recovered from the loop, and obtains the corresponding output according to the phase relationship between the clock signal and the data signal. It has important applications in phase-locked loops and clock recovery circuits. In integrated circuits, frequency and phase detectors are mainly divided into two categories: one is the PFD based on a periodic signal (clock), and the other is a PFD based on a pseudo-random signal. Of course, since the clock can be regarded as a special data signal, generally clock-based PFD is not suitable for data signals, but data-based PFD can be applied to clock signals, and...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/087H03L7/08H03L7/099
CPCH03L7/0807H03L7/087H03L7/0995
Inventor 张长春王新稳
Owner NANJING UNIV OF POSTS & TELECOMM
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