A shift-based instruction extraction and buffering method and superscalar microprocessor

An instruction extraction and buffering method technology, applied in concurrent instruction execution, electrical digital data processing, instruments, etc., can solve problems such as the number of valid instructions is not fixed, the extraction and buffering cannot be processed in a fixed way, and the selection logic is complex. Achieve the effect of reducing overhead, simple extraction logic and buffering logic, simple and easy logic

Active Publication Date: 2018-12-28
飞腾技术(长沙)有限公司 +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The difficulty is that the number of effective instructions is not fixed, and cannot be processe

Method used

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  • A shift-based instruction extraction and buffering method and superscalar microprocessor
  • A shift-based instruction extraction and buffering method and superscalar microprocessor
  • A shift-based instruction extraction and buffering method and superscalar microprocessor

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Embodiment Construction

[0031] Such as figure 2 As shown, the implementation steps of the shift-based instruction fetching and buffering method in this embodiment include:

[0032] 1) Construct a valid word mask for the instruction word, if the mask is true, the instruction word is valid, otherwise, the instruction word is invalid;

[0033] 2) Perform a right-aligned shift on the instruction line according to the instruction word offset;

[0034] 3) Split the shifted instruction line according to the word width according to the effective word mask and extract the effective word;

[0035] 4) Sort the valid words into the buffer block sequence;

[0036] 5) The buffer block sequence is written into the buffer queue controlled by the write enable of the buffer item.

[0037] The shift-based instruction extraction and buffering method of this embodiment constructs an effective word mask according to the prediction offset provided by the branch prediction information and the instruction word offset pro...

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Abstract

The invention discloses an instruction extracting and buffering method based on shift and a superscalar microprocessor, A method for extracting and buffering includes steps: a valid word mask is constructed for an instruction word, a right-aligned shift is carried out on the instruction line according to the instruction word offset, the shifted instruction line is split according to the word widthaccording to the effective word mask and the effective word is extracted, the effective word is sorted into a buffer block sequence, and the buffer block sequence is written into the buffer queue bythe buffer entry write enable control buffer block sequence; a superscalar microprocessor include instruction fetch and buffer logic component programmed to perform that aforementioned instruction fetch and buffer methods. The invention is simpler and easier to realize than the traditional logic through the design of instruction line shift, instruction word sorting and writing buffer queue by buffer block sequence, which can ensure the high efficiency of instruction fetching, also makes the fetching logic and buffer logic simpler, and reduces the hardware overhead.

Description

technical field [0001] The invention relates to the field of microprocessors, in particular to a shift-based instruction extraction and buffering method and a superscalar microprocessor. Background technique [0002] A superscalar microprocessor can send multiple instructions to each execution unit per cycle to increase the total processing capacity of the processor. This requires the instruction fetch unit and decoding unit at the front end of the microprocessor pipeline to efficiently provide instruction streams to execution unit. Therefore, the instruction fetch unit of the microprocessor must have a corresponding logic circuit to process the instruction byte stream entering the pipeline, determine the start boundary of the instruction word and extract the effective instruction word, so that it can enter the decoding unit or instruction word as soon as possible. buffer queue. [0003] In processor design, the traditional technology is to extract and buffer effective ins...

Claims

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Application Information

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IPC IPC(8): G06F9/302G06F9/38
CPCG06F9/30018G06F9/3806
Inventor 王小岛赵天磊高军王玉姣苑佳红薛洪波刘晓燕李文哲孙龙鹏丁哲曹文辉郑帅克
Owner 飞腾技术(长沙)有限公司
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