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an accelerator interface

An accelerator and interface technology, applied in the field of accelerator interface, can solve the problems of low transmission rate, low applicability and high delay, and achieve the effect of strong applicability, high bandwidth and low delay

Active Publication Date: 2021-07-23
北京融芯微科技有限公司
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  • Abstract
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AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is the technical problem of low applicability, low transmission rate and high delay existing in the prior art

Method used

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Embodiment 1

[0032] This embodiment provides an accelerator interface, such as figure 1 , the accelerator interface is connected between the server and the accelerator; the accelerator interface is a DDR interface, the DDR interface includes a DDR storage module, and a high-speed switch for controlling the sharing or disconnection of the DDR memory unit, and the accelerator interface adopts the DDR address and The command signal sequence completes the data communication between the server and the accelerator.

[0033] The accelerator of this embodiment adopts FPGA, and DDR memory unit replaces DRAM. The rest are similar to this embodiment and will not be described again. DDR interface can adopt DDR3 or DDR4.

[0034] Since the DDR interface does not have an interrupt interaction mechanism, this embodiment uses a DDR address and a special sequence of command signals to communicate between the server and the accelerator. This special sequence uses the unique sequence set by CAS LATENCY in ...

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Abstract

The invention relates to an accelerator interface, which solves the technical problems of low applicability, low transmission rate and high delay, and is connected between a server and an accelerator by using the accelerator interface; the accelerator interface is a DDR interface, and the DDR interface includes a DDR storage module, and a high-speed switch that controls the sharing or disconnection of DDR memory units. The accelerator interface uses the DDR address and command signal sequence to complete the data communication between the server and the accelerator. This problem is better solved and can be used for accelerators and accelerators. server or server connection.

Description

technical field [0001] The invention relates to the field of accelerators, in particular to an accelerator interface. Background technique [0002] Artificial intelligence requires machine learning and fast calculations with intelligent algorithms. General-purpose computers are insatiable and require various types of accelerators. Accelerators require high transfer rates and low latency. Graphics Processing Unit (GPU for short) and Field Programmable Gate Array (Field-Programmable Gate Array, FPGA for short) are the most important algorithm accelerators. [0003] At present, the interface between the accelerator and the server is the bus interface PCI express, and the maximum bandwidth of the bus interface PCIexpress is 16MB / s. Moreover, the high-bandwidth PCI express is generally used in high-end server central processing units (Central Processing Unit, CPU for short). Therefore, existing accelerator interfaces have the technical problems of poor adaptability of high-pe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/16
CPCG06F13/16
Inventor 林琦杨艳萍
Owner 北京融芯微科技有限公司
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