LSTM (Long Short-Term Memory) forward direction operation accelerator based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a LSTM (Long Short-Term Memory) forward direction operation accelerator based on an FPGA (Field Programmable Gate Array), and works by a hardware and software coordination pattern. A hardware part contains three types of accelerator designs: a single-DMA (Direct Memory Access) pattern LSTM neural network forward direction algorithm accelerator, a double-DMA pattern LSTM neural network forward direction algorithm accelerator and a spare LSTM neural network forward direction algorithm accelerator. The accelerator is used for accelerating a LSTM network forward direction calculation part and comprises a matrix-vector multiplication module, an Element-wise operation module and an activation function module. The single-DMA pattern accelerator has a good operation effecton the aspects of performance and an energy efficiency ratio. The double-DMA pattern accelerator and the sparse network accelerator have the good effect on the aspect of the energy efficiency ratio, and in addition, more on-chip storage resources of the FPGA can be saved.

Description

technical field [0001] The invention relates to the field of computer hardware acceleration, in particular to an FPGA-based LSTM forward operation accelerator and a design method thereof. Background technique [0002] Long short-term memory (LSTM) network is currently the most mainstream variant of recurrent neural network (RNNs), which solves the long-term dependence problem faced by traditional recurrent neural network algorithms in practical tasks. Based on the characteristics of the LSTM network, it is widely used in the fields of speech recognition, machine translation and image processing. Since the LSTM neural network contains a large number of parameters, the operation process is a calculation-intensive operation. Using a general-purpose hardware platform such as a CPU to execute the LSTM algorithm does not perform well in terms of computing performance and energy consumption. Therefore, using dedicated hardware accelerators to improve the computing performance of L...

AI Technical Summary

Problems solved by technology

But ASIC also has disadvantages: the programming development cycle is long, and it cannot be modified after the circuit logic design and manufacture are completed, and if the logic needs to be modified, it must be redesigned

Nowadays, the research on neural network algorithms is constantly innovating, so the poor design flexibility of ASIC limits its promotion in the field of scientific research

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