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Memory and forming method thereof

A memory, channel direction technology, applied in the direction of electric solid devices, semiconductor devices, electrical components, etc., can solve the problem of poor performance of split-gate flash memory, avoid the decline of electron retention ability, improve erasing efficiency, avoid sharp The effect of a too small angle

Active Publication Date: 2018-09-04
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
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Problems solved by technology

[0004] However, the performance of existing split-gate flash memory is poor

Method used

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  • Memory and forming method thereof
  • Memory and forming method thereof

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Experimental program
Comparison scheme
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Embodiment Construction

[0022] As mentioned in the background, the performance of the memory formed by the prior art is relatively poor.

[0023] Figure 1 to Figure 3 It is a schematic diagram of the structure of a memory formation process.

[0024] refer to figure 1 , providing a semiconductor substrate 100, the semiconductor substrate 100 includes an erasing region X1 and a floating gate region X2, the floating gate region X2 is adjacent to the erasing region X1 and is located on both sides of the erasing region X1; The erasing gate structure 130 on X1, the floating gate structure 110 respectively located on the floating gate region X2, and the sidewall 120 located on the floating gate structure 110, the floating gate structure 110 has a back erase in the channel direction. In addition to the first sidewall 1111 of the gate structure 130, the sidewall 120 has a second sidewall 1201 facing away from the erase gate structure 130 in the channel direction; An isolation film 140 is formed on the out...

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Abstract

A memory and a forming method are disclosed. The forming method comprises: forming an erase gate structure, a floating gate structure, and a sidewall on the floating gate structure, wherein the floating gate structure and the sidewall are corresponding to a first side wall and a second side wall opposite to the erase gate structure in the channel direction respectively, the first side wall is planar, the first side wall is recessed toward the erasing gate structure with respect to the second side wall, and the first side wall and the second side wall are discontinuous; forming an isolation film on outer surfaces of the erase gate structure, the floating gate structure and the sidewall, and a surface of a semiconductor substrate, the isolation film covering the first side wall and the second side wall; forming a barrier film on a surface of the isolation film; etching the barrier film to expose the isolation film on the surface of the semiconductor substrate, and forming a barrier layercovering the first side wall and the second side wall; etching the isolation film with the barrier layer as a mask to expose the surface of the semiconductor substrate, and forming an isolation layercovering the first side wall and the second side wall; and removing the barrier layer. The method improves the performance of the memory.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a memory and a forming method thereof. Background technique [0002] Flash memory is an important device in integrated circuit products. The main feature of flash memory is that it can keep stored information for a long time without applying voltage. Flash memory has the advantages of high integration, fast access speed and easy erasing, so it is widely used. [0003] Flash memory is classified into two types: stack gate flash memory and split gate flash memory. The stacked gate flash memory has a floating gate and a control gate above the floating gate. The stacked gate flash memory has the problem of over-erasing. Different from the stacked gate flash memory, the split gate flash memory forms a word line as an erasing gate on one side of the floating gate. The split-gate flash memory can effectively avoid the over-erasing effect. [0004] However, the existing s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11517H10B41/00
CPCH10B41/00
Inventor 于涛王百钱
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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