A conversion control circuit of mipi C-Phy TX output state

Abstract

The present application provides a conversion control circuit for the output state of the MIPI C-Phy TX terminal, including a primary circuit, a secondary circuit, a tertiary circuit and a drive control circuit. The first-level circuit is used to output Flip signal, Rotation signal and Polarity signal according to the character signal and working clock signal output by the parallel-to-serial conversion circuit of MIPI; signal, working clock signal and reset control signal to output A signal, B signal and C signal; the three-stage circuit is used to output the first The output signal, the second output signal and the third output signal; the driving control circuit is used for encoding the first output signal, the second output signal and the third output signal to obtain the conversion control signal. This circuit enables the character signal output by the parallel-to-serial conversion circuit to be effectively converted into the state on the transmission line and output to the RX terminal.

Description

technical field [0001] The present application relates to the technical field of mobile communication, and more specifically, relates to a conversion control circuit of the output state of the MIPI C-Phy TX terminal. Background technique [0002] MIPI (mobile industry processor interface) is a mobile industry processor interface, an open standard and specification initiated by the MIPI Alliance for processors used in mobile devices. C-Phy is the latest interface protocol of MIPI. Unlike the D-Phy and M-Phy before MIPI, which uses a differential signal transmission method consisting of two wires, C-Phy uses three wires to transmit signals, and the voltages on the three wires are different. , get different online status Wire State. The TX end will map the conversion layer 21bit data according to the 16bit real data that needs to be transmitted through the lookup table, and 21bit contains 7 characters symbol. If it is necessary to transmit the 7 symbols to the RX terminal, th...

AI Technical Summary

Problems solved by technology

The idea of ​​this scheme is the simplest, but the hardware overhead is high. For example, the symbols of the two clock cycles before and after have a total of 6 bits, and the permutations and combinations have a total of 2 bits. 6 = 64 arrangements, considering the actual C-PHY protocol, each symbol has 5 possible values, so there are 5 × 5 = 25 combinations, so the combination logic of the encoding circuit requires 25 input ports, corresponding to 25 input data combination, the circuit scale is relatively large

Moreover, the more complex the combinational logic, the more it will affect the fastest frequency of the entire circuit, thereby reducing the bandwidth of the entire transmission interface

Both scheme 1 and scheme 2 are theoretically feasible. According to these two ideas, the circuit function can be finally realized, but the cost will be too high

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