MIPI C-Phy TX output state conversion control circuit

Abstract

The invention provides an MIPI C-Phy TX output state conversion control circuit. The conversion control circuit comprises a first-stage circuit, a second-stage circuit, a third-stage circuit and a driver control circuit. The first-stage circuit is used for outputting a Flip signal, a Rotation signal and a Polarity signal according to a character signal and a work clock signal output by a parallel-serial conversion circuit of an MIPI; the second-stage circuit is a ring circuit; the ring circuit is used for outputting an A signal, a B signal and a C signal according to the Flip signal, the Rotation signal, the Polarity signal, the work clock signal and a reset control signal; the third-stage circuit is used for outputting a first output signal, a second output signal and a third output signal according to the A signal, the B signal, the C signal, the work clock signal and the reset control signal as an initial value; and the driver control circuit is used for performing coding processingon the first output signal, the second output signal and the third output signal to obtain conversion control signals. The circuit ensures that the character signal output by the parallel-serial conversion circuit can be effectively converted into a state on a transmission line and output to an RX end.

Description

technical field [0001] The present application relates to the technical field of mobile communication, and more specifically, relates to a conversion control circuit of the output state of the MIPI C-Phy TX terminal. Background technique [0002] MIPI (mobile industry processor interface) is a mobile industry processor interface, an open standard and specification initiated by the MIPI Alliance for processors used in mobile devices. C-Phy is the latest interface protocol of MIPI. Unlike the D-Phy and M-Phy before MIPI, which uses a differential signal transmission method consisting of two lines, C-Phy uses three lines to transmit signals, and the voltages on the three lines are different. , get different online status Wire State. The TX end will map the conversion layer 21bit data according to the 16bit real data that needs to be transmitted through the lookup table, and 21bit contains 7 characters symbol. If it is necessary to transmit the 7 symbols to the RX terminal, th...

AI Technical Summary

Problems solved by technology

The idea of ​​this scheme is the simplest, but the hardware overhead is high. For example, the symbols of the two clock cycles before and after have a total of 6 bits, and the permutations and combinations have a total of 2 bits. 6 = 64 arrangements, considering the actual C-PHY protocol, each symbol has 5 possible values, so there are 5 × 5 = 25 combinations, so the combination logic of the encoding circuit requires 25 input ports, corresponding to 25 input data combination, the circuit scale is relatively large

Moreover, the more complex the combinational logic, the more it will affect the fastest frequency of the entire circuit, thereby reducing the bandwidth of the entire transmission interface

Both scheme 1 and scheme 2 are theoretically feasible. According to these two ideas, the circuit function can be finally realized, but the cost will be too high

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