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Trigger automatic layout method and apparatus

An automatic layout and flip-flop technology, which is applied in the direction of instruments, special data processing applications, electrical digital data processing, etc., can solve the problems of increasing the clock power consumption of the local clock system and affecting the performance of the local clock system

Active Publication Date: 2018-05-25
LOONGSON TECH CORP
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Problems solved by technology

[0005] The present invention provides a flip-flop automatic layout method and device, which are used to solve the phenomenon of overlap of flip-flop classes that still exists after multiple clustering of each flip-flop class in the prior art, which in turn affects the performance of the local clock system , the problem of increasing the clock power consumption of the local clock system

Method used

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  • Trigger automatic layout method and apparatus
  • Trigger automatic layout method and apparatus
  • Trigger automatic layout method and apparatus

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specific Embodiment approach

[0077] Alternatively, another specific implementation manner of step 1035 includes:

[0078] According to the actual size of each trigger class, determine the first preset constraint relationship |x between each trigger class a -y b |+|y a -y b |≥(h a + h b ) / 2+(w a +w b ) / 2, and the third preset constraint relationship h between each trigger class c ≥h′ c N c ,w c ≥w′ c N c , where N cis the number of triggers in the cth trigger class;

[0079] Under the constraints of the first preset constraint relationship and the third preset constraint relationship, determine the movement coordinate information (x a ,y a ).

[0080] In this embodiment, specifically, first determine a preset constraint relationship, in the preset constraint relationship, and the x-axis movement distance constraint condition of each trigger type, the y-axis movement distance constraint condition of each trigger type, each trigger Under the constraints of the number of paths between trigger...

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Abstract

The invention provides a trigger automatic layout method and apparatus. The method comprises the steps of performing clustering analysis on triggers according to attribute information of the triggers,and classifying the triggers into at least one trigger class, wherein the trigger class comprises at least one trigger; moving the trigger classes to reduce a contact area between the trigger classes; according to original coordinate information of the trigger classes before the trigger classes are moved, coordinate information of the trigger classes after the trigger classes are moved, and a preset constraint relationship, determining moving coordinate information of the trigger classes, thereby determining moving positions of the trigger classes; moving the triggers in the trigger classes to determine trigger layouts in the trigger classes; and repeating the steps until the trigger classes meet a preset condition of reducing overlapping of the trigger classes. The overlapping phenomenonof the trigger classes can be reduced; the performance of a local clock system is enhanced; and the clock power consumption of the local clock system is reduced.

Description

technical field [0001] The invention relates to semiconductor integrated circuit technology, in particular to a flip-flop automatic layout method and device. Background technique [0002] In the field of integrated circuit design, the clock system is an important part of the integrated circuit, and in the design of high-performance integrated circuits, the clock system is divided into a global clock system, a regional clock system and a local clock system. The local clock system is connected with the sequential unit flip-flops of the integrated circuit to form a sub-clock tree; the distribution of flip-flops directly affects the performance of the local clock system. In the local clock system, the distribution of flip-flops is required to have a certain regularity or spatial consistency. The regular design of flip-flops is conducive to optimizing the bus length of the local clock system, reducing the clock power consumption of the local clock system, and meeting the requirem...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/392
Inventor 王昊杨梁
Owner LOONGSON TECH CORP
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