Electrostatic protection device based on SOI (Silicon-On-Insulator) technology and formed electrostatic protection circuit

Abstract

The invention provides an electrostatic protection device based on a SOI (Silicon-On-Insulator) technology and a formed electrostatic protection circuit. The device is a GGNMOS with a multiple parallel structure, and comprises a buried oxide layer, a P well area, a source, a drain, a gate, a P+ contact area and a pseudo gate, wherein the P+ contact area is arranged at one side, far away from the drain, of the source; the P+ contact area is separated from the source through the P well area; and the pseudo gate covers the P well area between the P+ contact area and the source. Thus, the reverseESD protection capability can be improved.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to an SOI technology-based electrostatic protection device and an electrostatic protection circuit formed thereof. Background technique [0002] Electrostatic protection (ESD) is an important link in integrated circuit (IC) design. As the technology becomes more and more advanced, especially in the new SOI (Silicon-On-Insulator, silicon on insulator) process, due to the buried oxide BOX), the thickness of the top silicon (Si) is much thinner than that of traditional CMOS technology, and the ESD current is usually very large, which makes it more difficult to discharge the ESD current, and the current tends to concentrate to make the heat dissipation problem more serious. Therefore, the device is more likely to be burned, causing its ESD protection capability to become a major bottleneck. [0003] Such as figure 1 As shown, it is a commonly used Gate-Ground NMOS (GGNMOS for short)...

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Problems solved by technology

[0005] When a negative ESD pulse is applied to the drain 4 and the source is grounded, the source-P well forms a reverse-biased PN junction, and the P-well-drain forms a forward-biased PN junction. The conduction mechanism is the same as that described in the previous section. It means that the parallel structure is triggered as uniformly as possible, and the width of the source 3 also needs to be elongated, which requires more layout area

[0006] To sum up, the ESD protection of the traditional GGNMOS structure mainly relies on parasitic NPN, and the discharge capacity per unit size of the parasitic NPN is small, resulting in insufficient ESD protection capability.

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