Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Non-blocking parallel triangle rasterization unit structure

A unit structure and triangle technology, which is applied in the field of non-blocking parallel triangle rasterization unit structure, can solve the problems of GPU functions and performance cannot be fully utilized, commercial GPU chip replacement is fast, and the portability is poor, so as to improve the pixel generation ability and realize Effects of improved processing performance and scanning performance

Active Publication Date: 2018-05-08
XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
View PDF8 Cites 13 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, there is no GPU based on a unified dyeing architecture in my country, and a large number of commercial GPU chips imported from abroad are used in display control systems in various fields.
Especially in the military field, foreign imported commercial GPU chips have poor temperature and environmental adaptability, cannot guarantee that the circuit itself or supporting software has no "back door", contains a large number of redundant functional units that are not needed in the military field, and the power consumption index cannot meet the requirements. Commercial GPU chips are updated quickly, facing production stoppages and outages at any time, making it difficult to meet defects such as continuous support of weapons and equipment, and there are major hidden dangers in terms of safety, reliability, and support.
Moreover, due to political, military, economic and other reasons, foreign countries have implemented technology "blockade" and product "monopoly" on my country, making it difficult to obtain the underlying technical information of GPU chips, such as register information, detailed internal micro-architecture, core software source code, etc., resulting in GPU functions and performance cannot be fully utilized, and the portability is poor; the above problems seriously restrict the independent research and development of display systems in my country

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Non-blocking parallel triangle rasterization unit structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0020] A non-blocking parallel triangle rasterization unit structure of the present invention is composed of 7 functional pipeline stages, and the 7 functional pipeline stages are a triangle vertex receiving unit, a triangle scanning parameter establishing unit, and an edge function method in sequence from front to back The Tile scanning unit, the boundary Tile pixel position relationship determination unit, the boundary Tile pixel anti-aliasing unit, the Tile attribute interpolation request arbitration unit and the Tile attribute interpolation unit are connected in order from front to back, and the data output of the previous pipeline level is used as the next one. Pipeline-level data input.

[0021] The triangle vertex receiving unit receives the vertex attribute transmission command sent from the outside of the rasterization unit, extracts the vertex attribute data in the command, stores it in the vertex attribute data buffer inside the unit, and then transfers the vertex at...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a non-blocking parallel triangle rasterization unit structure. The triangle rasterization unit structure consists of 7 functional pipeline stages, which are a triangle vertex receiving unit, a triangle scanning parameter establishment unit, an edge function method Tile scanning unit, a boundary Tile pixel position relation judgment unit, a boundary Tile pixel anti-aliasing unit, a Tile attribute interpolation request arbitration unit and a Tile attribute interpolation unit in sequence from front to back. The triangle rasterization unit structure has capabilities of non-blocking parallel triangle block scanning and processing; pixel Tiles covered by a triangle are classified into two types including Tiles completely in the triangle and Tiles partially in the triangle;two parallel processing channels are set; on the premise of keeping a triangle Tile output sequence, non-blocking parallel scanning of the two types of the Tiles can be realized; the resource utilization rate, the triangle processing capability and the pixel generation capability are improved; and especially for relatively large triangle primitives, the structure is more effective.

Description

technical field [0001] The invention belongs to the technical field of computer hardware and relates to a non-blocking parallel triangle rasterization unit structure. Background technique [0002] With the continuous increase of graphics applications, the early solution of graphics rendering by CPU alone has been difficult to meet the graphics processing needs of performance and technology growth, and the graphics processing unit (Graphic Processing Unit, GPU) came into being. Since the release of the first GPU product by Nvidia in 1999, the development of GPU technology has mainly gone through the fixed-function pipeline stage, the stage of separating the dyer architecture, and the stage of unified dyer architecture. Rendering gradually extends to the field of general computing. The high-speed, parallel features and flexible programmability of the GPU pipeline provide a good operating platform for graphics processing and general parallel computing. [0003] At present, th...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06T1/20
CPCG06T1/20
Inventor 张骏任向隆韩立敏郑新建裴希杰
Owner XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products