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Fractional order delay realization method based on sampling control separation principle

A technology that separates principles and implementation methods, and is applied in adaptive control, general control systems, control/regulation systems, etc. It can solve problems that are not solutions, and achieve the effect of simple design, high resolution, and high fractional delay

Active Publication Date: 2018-04-27
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The previous implementation scheme has been realized by interpolation method and FIR principle, but this scheme is an approximate fitting scheme, there will be high-frequency attenuation in the amplitude, and the signal cannot be kept straight through in the whole frequency band; and its accuracy and the required memory resources are mutually restricted, and it is impossible to use less memory resources to achieve high-precision fractional delay links
So the previous solution is not an optimal solution

Method used

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  • Fractional order delay realization method based on sampling control separation principle
  • Fractional order delay realization method based on sampling control separation principle

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specific Embodiment 1

[0024] Specific embodiment one: for the digital control system that the fractional order delay link and the integer order link are connected in series

[0025] At a controller output update frequency f s_control In a 10kHz digital control system, if it is necessary to implement a 0.3 beat fractional delay link and the fractional delay link and the integer order part are connected in series, since the order of the series links of the control system can be exchanged, the This fractional delay link is equivalent to the fractional delay sampling of the input, that is, the input is 0.3*T s_control =0.3*1 / f s_control = 0.03ms delay sampling; set a f in the microprocessor timer = The 100kHz timer is used as a fractional timer, and the fractional timer is started at the beginning of each control algorithm cycle. The timing delay time γ of this timer is 0.03ms (three timer periods, 3*1 / f timer =3*T timer =3*0.01ms=0.03ms), that is, the timer counts three times; the fractional order...

specific Embodiment 2

[0026] Specific embodiment two: the numerical control system that is used for the digital control system that the fractional order leading link and the integer order link are serial relations

[0027] In some digital control systems (such as: repetitive controllers), it is necessary to realize the fractional-order lead link. If the fractional-order lead link and the integer-order link are connected in series, the realization of the fractional-order lead link can be converted into a fractional-order delay link. The realization of a digital control system with a fractional lead link, such as its controller output update frequency f s_control is 10kHz, it is necessary to implement a 0.3-beat fractional-order lead link, and this 0.3-beat fractional-order lead link is equivalent to a (1-0.3=0.7) beat fractional-order delay link and a 1-beat lead link, and the problem is transformed into input The 0.7 beat fractional delay sampling of the quantity, that is, the input quantity is 0.7...

specific Embodiment 3

[0028] Specific embodiment three: a digital control system comprising multiple fractional delay links and / or multiple fractional lead links

[0029] The present invention can also be applied to digital control systems with multiple fractional delays or fractional advances, where a controller outputs an update frequency f s_controlThe 10kHz digital control system includes a 0.3-beat fractional-order lead link, a 0.4-beat fractional-order delay link, and a 0.5-beat fractional-order delay link, and these three fractional-order links are connected in series with integer-order links, that is, three Each fractional-order link can be transformed into a fractional-order sampling of the input. Three fractional steps need to use three timers to trigger sampling. If the timer resources of the microprocessor are relatively tight, you can also put three delays in one timer, and then trigger three samples of the input. i.e. need delay γ 1 , gamma 2 , gamma 3 to trigger sampling, γ 1 =(...

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Abstract

The invention discloses a fractional order delay realization method based on a sampling control separation principle, which belongs to the technical field of control theories and signal processing. According to the sampling control separation principle, a high-speed timer of a microprocessor is used to generate fixed delay to trigger sampling to realize fractional order delay sampling, a fractional order delay link is further realized, the timer is adopted to count the fixed delay after each control period begins and triggers a sampling module to carry out fractional order delay sampling on input at the expiration of the fixed delay, the fixed delay can be determined according to a product between the fractional order delay beat number and the control period, the fractional order signals sampled in a former period are used for calculation in a next controller calculation period, the following other realization is similar to realization of the traditional control system, the design is simple, too many parameters do not need to be calculated, and an approximate fitting condition does not exist.

Description

technical field [0001] The invention discloses a method for realizing fractional time delay based on the separation principle of sampling control, and belongs to the technical field of control theory and signal processing. Background technique [0002] In digital control systems, especially in control systems with low control update frequency, it is often necessary to implement a fractional delay link. The previous implementation scheme has been realized by interpolation method and FIR principle, but this scheme is an approximate fitting scheme, there will be high-frequency attenuation in the amplitude, and the signal cannot be kept straight through in the whole frequency band; and its accuracy and the required memory resources are mutually restricted, and it is impossible to use less memory resources to achieve high-precision fractional delay links. So the previous solution is not an optimal solution. This application aims to propose a solution that can realize high-preci...

Claims

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Application Information

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IPC IPC(8): G05B13/04
CPCG05B13/042
Inventor 武玉衡叶永强何顺华
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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