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A display device with a high-speed interface

A display device and interface technology, applied to static indicators, cathode ray tube indicators, instruments, etc., can solve the problems of unstable signal synchronization function, inflexible interface configuration, high clock frequency of low-voltage differential transmission, etc., to improve clock quality , Guaranteed performance and reduced power consumption

Active Publication Date: 2020-03-10
LUMICORE MICROELECTRONICS SHANGHAI CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to support higher display resolution and refresh rate, micro-displays based on silicon chips use LVDS interface, which has the disadvantages of inflexible interface configuration, high low-voltage differential transmission clock frequency, and unstable signal synchronization function. Display driving method for pixel transmission

Method used

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  • A display device with a high-speed interface
  • A display device with a high-speed interface
  • A display device with a high-speed interface

Examples

Experimental program
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Effect test

no. 1 example

[0032] combined with figure 1 , this embodiment describes a display device with a high-speed interface.

[0033] The device includes an image generator 101 , a display 201 and a set of low-voltage differential signal transmission lines connecting the image generator 101 and the display 201 , including a first low-voltage differential signal transmission line 301 and a second low-voltage differential signal transmission line 302 .

[0034] The image generator 101 includes at least an image data generation module 102 , a first low voltage differential interface 111 , a second low voltage differential interface 112 , a first serial-to-parallel converter 114 , and a first clock generator 131 .

[0035] The display 201 includes at least a third low-voltage differential interface 211, a fourth low-voltage differential interface 212, a second serial-to-parallel converter 214, a second clock generator 231, a synchronization circuit 215, a row driver circuit 262, a column driver circui...

no. 2 example

[0047] This embodiment is basically the same as the first embodiment, the special features are:

[0048] Further, both the first clock generator 131 and the second clock generator 231 are phase-locked loops, the ratio of the output clock frequency of the phase-locked loop to the output clock frequency is M / N, and both M and N are greater than or equal to 1 An integer, preferably 8-32, selected according to the internal configuration registers or input pins of the display 201 . There is a voltage-controlled oscillator inside the phase-locked loop, and both the oscillation voltage and the reference current are generated by the internal circuit of the phase-locked loop. The power supply of the phase-locked loop circuit is 1.2 ~ 3.3V. The frequency of the first output clock 153 of the first clock generator 131 is S times the frequency of the second output clock 253 of the second clock generator 231, and S is equal to M / N. The input clock (reference clock) 152 of the first clock ...

no. 3 example

[0051] This embodiment is basically the same as the first embodiment, the special features are:

[0052] Further, both the first clock generator 131 and the second clock generator 231 are phase-locked loops, the ratio of the output clock frequency of the phase-locked loop to the output clock frequency is M / N, and both M and N are greater than or equal to 1 An integer, preferably 8-32, selected according to the internal configuration registers or input pins of the display 201 . There is a voltage-controlled oscillator inside the phase-locked loop, and both the oscillation voltage and the reference current are generated by the internal circuit of the phase-locked loop. The power supply of the phase-locked loop circuit is 1.2 ~ 3.3V. The frequency of the first output clock 153 of the first clock generator 131 is S times the frequency of the second output clock 253 of the second clock generator 231, and S is equal to M / N. The input clock (reference clock) 152 of the first clock ...

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Abstract

The invention discloses a display device with high-speed interfaces, which includes an image generator, a display, and low-voltage differential signal transmission line groups connecting the image generator and the display. A light emitting device is located over a pixel array circuit. A first low-voltage differential interface and a third low-voltage differential interface are connected by a first low-voltage differential signal transmission line group. A second low-voltage differential interface and a fourth low-voltage differential interface are connected by a second low-voltage differential signal transmission line group. The first low-voltage differential interface and the third low-voltage differential interface each include group-divisible data interfaces, which include a pixel datainterface, a row and column control signal interface and a synchronization signal interface. By dividing pixel data into multiple groups of extendable pixel data differential transmission interfacesand transmission signal groups and using a flexible variable-frequency clock generator, the flexibility of interface configuration is improved, the transmission frequency of clock signals is reduced,the clock quality is improved, the power consumption is reduced, and the stability of synchronization signals is enhanced.

Description

technical field [0001] The invention relates to the technical field of flat displays, in particular to a high-speed transmission circuit for micro-displays with silicon chips as substrates. Background technique [0002] Most of the traditional micro-displays with silicon chips as the substrate use transmission interfaces based on analog voltage ranges (such as VGA interfaces, AV interfaces, etc.) or transmission interfaces based on digital logic levels (such as digital RGB interfaces, etc.), and the data transmission speed is limited. . Conventional flat-panel displays use interfaces such as DVI, HDMI, Display Port, and MIPI, and require dedicated codec chips. Microdisplays based on semiconductor silicon chips need to integrate interface circuits into semiconductor silicon chip substrates. The dedicated codec chips used in conventional flat panel displays are not suitable for microdisplays based on silicon chips due to process compatibility and other issues. In order to su...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G09G5/00
CPCG09G5/006
Inventor 季渊陈文栋黄舒平王成
Owner LUMICORE MICROELECTRONICS SHANGHAI CO LTD
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