Spice simulation method including ip/memory timing path

Abstract

Provided is a spice simulation method containing an IP / Memory timing path. The method comprises the following steps: reading a IP / Memory-containing timing library file under a current technological condition and analyzing timing edges of input and output pins of each IP / Memory; reading a key path and a corresponding Spice Deck file and finding out an IP / Memory device in the key path; creating a Verilog-A model from given two-dimensional list information of the timing library file according to a timing edge of the Spice Deck in order to obtain time delay and output jump values of the device andobtaining capacitance values of the pins from the timing library file, and adding above values into the spice; taking the Verilog-A model into the Spice Deck so as to simulate an overall path. According to the method, simulation speed is increased evidently without affecting precision. Therefore, multiple paths containing IP / Memory can be simulated and can be widely accepted by many engineers inactual application.

Description

technical field [0001] The invention relates to the technical field of electronic design automation (EDA), in particular to a spice simulation method including an IP / Memory timing path. Background technique [0002] In the process of integrated circuit design, timing analysis and sign-off are usually done using static timing analysis (STA), but as the technology becomes more and more advanced, the results of STA will become unreasonable. In particular, the deviation of the process cannot be accurately reflected, which will affect the entire chip design cycle and the yield rate of the final product. [0003] In response to the above problems, more and more engineers use spice simulation to complete timing analysis and sign-off. The timing quality of the entire chip is ensured by simulating the critical path. In addition, it can be simulated at any voltage, and its accuracy and flexibility have obvious advantages over the STA method. [0004] However, the existing spice simu...

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Problems solved by technology

[0004] However, the existing spice simulation also has obvious shortcomings, such as the speed is generally slow, the required spice netlist is not easy to generate, and the timing path with IP / Memory cannot be simulated, etc.

Especially the third item, the reason is that the complete circuit netlist of IP is often not provided, and even if it is provided, the entire timing path cannot be simulated

This restricts the application of spice simulation to a large extent

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