Application verification plate of coprocessor

Abstract

The invention relates to an application verification achieving method which is suitable for a coprocessor. The method is mainly composed of a multiple power domain and single power supply design, a high-speed interface system integration and application verification design and a power supply consumption and high-speed signal testability design. By adoption of the application verification achieving method, the problems, such as insufficient power supply types and power supply capacity, low integrated speed and large power consumption power supply of a communication interface system and uncheckable high-speed signals, in an application verification plate of a traditional processor, are solved; the method can not only guarantee multiple power domain, large power consumption and single power supply of the coprocessor, but also complete system integration and application verification of multiple high-speed interfaces of the coprocessor; under the premise that the integrality of the power supply and signals is guaranteed, a testability design is achieved, under the premise that the design function of the coprocessor is fully verified, monitoring of power supply consumption and high-speed signals is completed, and the method provides the verification basis for the following design.

Description

technical field [0001] The invention relates to the fields of integrated circuit application verification and application development, in particular to an application verification board of a coprocessor. Background technique [0002] The coprocessor is the initial sample verification chip of the "twelfth five-year" nuclear high-base project "massive information processor". It mainly completes the verification of the main functional modules and design ideas in the massive information processor. It can also be used as a 16-core high-speed processors to market. Because the coprocessor is a new product in the pre-research project, there is no design for its application verification. Compared with the previously designed processor, in addition to UART, DSU, JTAG and other interfaces, the coprocessor adds a high-speed interface DDR2 / 3 controller interface, four 1X 2.5GHz rapidIO interfaces, DQR controller interface and PIU / EMIF and other interfaces, the working frequency is incr...

AI Technical Summary

Problems solved by technology

The previous low-speed interface design can no longer meet the needs of coprocessor application verification

Thirdly, for the testability design of the application verification board, when the power supply current is not large and the signal rate is not high, methods such as jumper selection, test holes, and reserved test points can be used to solve the problem. The current is above 14A, the memory interface is 400MHz, and the high-speed communication bus is 2.5Gbps. The original design can no longer guarantee the requirements of power supply capability, power integrity and signal integrity.

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