A Parallel Communication Method

Abstract

The invention discloses a parallel communication method. A bus for parallel communication is connected between a host computer and a slave computer and comprises an address data bus body, a reading-writing selection line and an enabling latching line; during communication, the host computer controls the level of the enabling latching line to be valid or invalid to get the slave computer into or out of the communication state; the host computer controls the level of the reading-writing selection line to enable the slave computer to learn that the host computer needs to write data or read data through the address data bus body; during data writing, the host computer changes the level of the reading-writing selection line to enable the slave computer to learn that the host computer completes data writing through the address data bus body so that written data output by the host computer can be input; during data reading, and the host computer changes the level of the reading-writing selection line to enable the slave computer to learn that the host computer completes releasing of the address data bus body so that read data can be output to the host computer. By means of the parallel communication method, the number of pins of the adopted host computer is small, the number of time sequence links is small, a time sequence is sufficient, logic conflicts are avoided, and user demands are met.

Description

technical field [0001] The invention relates to the field of digital circuit system communication, in particular to a parallel communication method. Background technique [0002] In recent years, many applications combine the master (such as MCU) with the slave (such as FPGA) to become the best partner. For example, MCU is responsible for low-speed functions such as system initialization, parameter and port configuration, and FPGA is responsible for high-speed functions such as data processing, access and transmission. Then the communication problem between MCU and FPGA becomes very prominent at this time. FPGA is a programmable device, the function of pins can be defined arbitrarily, and the number of pins is usually enough. Moreover, FPGA is essentially a kind of hardware, which can realize strict timing control. Therefore, the key point or bottleneck in designing the communication bus between MCU and FPGA lies in the characteristics of MCU. Since the existing MCU integ...

AI Technical Summary

Problems solved by technology

To sum up, there are two constraints in this method. First, the MCU is mainly used for control, and pins are one of the most precious resources of the MCU. Usually there are not too many pins for communication; second, the MCU uses the program The method of controlling the I / O port to simulate the bus timing is not the concurrent timing generated by the real logic circuit, and it cannot strictly control the timing matching between signals

[0003] There are more or less problems when the existing parallel bus communicates, and three kinds of various chip-level communication parallel buses commonly used are given as examples: 1) as Figure 5 and Image 6 The PC ISA bus shown has 30 bus pins, including address bus: A0-A15, data bus: D0-D15, control bus: CS#, RD#, WR#, and its advantage lies in the timing link Less, the disadvantage is that the number of bus pins is large; 2) such as Figure 7 and Figure 8 The MCS-51 microcontroller bus shown has 20 bus pins, including address / data bus: AD0-AD15, control bus: ALE, CS#, RD#, WR#, and its advantage lies in the number of bus pins Relatively few, the disadvantage is that there are many timing links; 3) if Figure 9 and Figure 10 The MEBI bus of the HCS12 single-chip microcomputer shown has 18 bus pins, including address / data bus: AD0-AD15, control bus: ECLK, R / W#. Less, the disadvantage is that there is a logical conflict (gray part)

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