Semiconductor chip aging test device and method

A chip aging test and aging test technology, which is applied in the direction of measurement device, electronic circuit test, measurement power, etc., can solve the problems of aging test accuracy and frequency distortion affecting semiconductor chips, achieve fast selection, and overcome impedance mismatch. , to ensure the effect of accuracy

Active Publication Date: 2017-10-20
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
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  • Claims
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Problems solved by technology

figure 2 It is a test signal schematic diagram of the test burn-in board 10 of the burn-in test device of the semiconductor chip of the prior art; figure 1 and figure 2 It can be seen that when the high-frequency signal of the high-frequency signal source is loaded to the semiconductor chip of the chip socket through the golden finger 14 of the test burn-in board 10, since the high-frequency signal source is input to the semiconductor chip installed in the chip socket through the signal transmission line 13, the high-frequency When the signal source is

Method used

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  • Semiconductor chip aging test device and method
  • Semiconductor chip aging test device and method
  • Semiconductor chip aging test device and method

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Embodiment 1

[0035] image 3 It is a structural schematic diagram of a test burn-in board of a burn-in test device for a semiconductor chip of the present invention; Figure 4 It is a schematic structural view of an embodiment of the burn-in testing device for semiconductor chips of the present invention; as Figure 3-4 As shown, in the semiconductor chip burn-in testing device provided in the first embodiment, the semiconductor chip is a flash memory. Of course, it may also be other types of semiconductor memory chips or other types of semiconductor chips, not limited to flash memory or memory. In this embodiment, the multiplexer MUX with two signal input terminals IN is selected to be used, that is, the multiplexer MUX that chooses one of the two. It is only used to perform burn-in tests on any two of the three modes of the write mode, read mode and erase mode of the semiconductor flash memory chip burn-in test device; wherein, the two signal input terminals IN of the multiplexer MUX ...

Embodiment 2

[0037] image 3 It is a structural schematic diagram of a test burn-in board of a burn-in test device for a semiconductor chip of the present invention; Figure 5 It is a schematic structural view of another embodiment of the burn-in testing device for semiconductor chips of the present invention; as image 3 , Figure 5 As shown, in the semiconductor chip burn-in testing device provided in the second embodiment, the semiconductor chip is a flash memory. Choose to use a multiplexer MUX with four signal input terminals IN, that is, a multiplexer MUX that selects one from four. The three signal input terminals IN of the multiplexer MUX described therein are connected with high-frequency crystal oscillators X of different frequencies, which are used for semiconductor flash memory in three modes of writing mode, reading mode and erasing mode The chip carries out the aging test of all modes. The multiplexer MUX in this embodiment refers to a multiplexer MUX with multiple signal...

Embodiment 3

[0044] The present embodiment three provides a semiconductor chip aging test method based on the above-mentioned embodiment one or embodiment two, adopts the semiconductor chip aging test device as above-mentioned embodiment one or embodiment two, and its scheme is as follows: through multiplexer The control circuit 200 composed of MUX and a plurality of high-frequency crystal oscillators X applies a frequency signal to the chip socket 102 of the test burn-in board 100, when the signal input terminal IN of the multiplexer MUX is connected with a high-frequency crystal oscillator X, and when the signal control terminal IN is strobe-connected with the signal input terminal IN of the high-frequency crystal oscillator X, the signal output terminal OUT of the multiplexer MUX outputs a certain high-frequency frequency test signal and load the test signal to the chip socket 102 of the test burn-in board 100, so as to perform burn-in test on the semiconductor chip to be burn-in tested ...

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Abstract

The invention provides a semiconductor chip aging test device and method. The device comprises an aging test board and a control circuit having a multiplexer and multiple high frequency crystal oscillators, when a signal input end of the multiplexer is connected with the high frequency crystal oscillators, a signal control end of the multiplexer is in gating connection with the signal input end, a signal output end of the multiplexer outputs a test signal which is loaded to a chip socket, and an aging test on a semiconductor chip is carried out. The device is advantaged in that a disadvantage of medium/high frequency signal transmission distortion in the prior art can be solved, selective input of multiple sets of signals having different frequencies is realized, and test accuracy and test efficiency are improved.

Description

technical field [0001] The invention relates to the field of semiconductor chip testing, in particular to a semiconductor chip aging testing device and method. Background technique [0002] The reliability test (HTOL, Endurance) and other durability aging tests of semiconductor chips in the prior art adopt the basic function test (Gross Function test), that is, the operating frequency of the chip will be reduced below 10Mhz, because the When the burn-in board transmits the high-frequency signal of the high-frequency signal source, the impedance of the high-frequency signal source does not match, which will cause distortion of the transmission line, resulting in abnormal high-frequency signal actually reaching the chip. figure 1 It is a structural schematic diagram of a test burn-in board of a semiconductor chip burn-in test device in the prior art, wherein the test burn-in board 10 includes a printed circuit board body 11 , a chip socket 12 , a signal transmission line 13 , ...

Claims

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Application Information

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IPC IPC(8): G01R31/28
CPCG01R31/2855
Inventor 曹巍周柯陈雷刚高金德
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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